LF-463-1: arm64/dts/imx8qm: Enable DPU in lpddr4 validation board
authorSandor Yu <Sandor.yu@nxp.com>
Fri, 13 Dec 2019 06:55:32 +0000 (14:55 +0800)
committerDong Aisheng <aisheng.dong@nxp.com>
Mon, 14 Dec 2020 03:21:39 +0000 (11:21 +0800)
Enable DPU in lpddr4 validation board.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts

index 79dba11..650bd81 100755 (executable)
        status = "okay";
 };
 
+&dc0_pc {
+       status = "okay";
+};
+
+&dc0_prg1 {
+       status = "okay";
+};
+
+&dc0_prg2 {
+       status = "okay";
+
+};
+
+&dc0_prg3 {
+       status = "okay";
+};
+
+&dc0_prg4 {
+       status = "okay";
+};
+
+&dc0_prg5 {
+       status = "okay";
+};
+
+&dc0_prg6 {
+       status = "okay";
+};
+
+&dc0_prg7 {
+       status = "okay";
+};
+
+&dc0_prg8 {
+       status = "okay";
+};
+
+&dc0_prg9 {
+       status = "okay";
+};
+
+&dc0_dpr1_channel1 {
+       status = "okay";
+};
+
+&dc0_dpr1_channel2 {
+       status = "okay";
+};
+
+&dc0_dpr1_channel3 {
+       status = "okay";
+};
+
+&dc0_dpr2_channel1 {
+       status = "okay";
+};
+
+&dc0_dpr2_channel2 {
+       status = "okay";
+};
+
+&dc0_dpr2_channel3 {
+       status = "okay";
+};
+
+&dpu1 {
+       status = "okay";
+};
+
+&dc1_pc {
+       status = "okay";
+};
+
+&dc1_prg1 {
+       status = "okay";
+};
+
+&dc1_prg2 {
+       status = "okay";
+
+};
+
+&dc1_prg3 {
+       status = "okay";
+};
+
+&dc1_prg4 {
+       status = "okay";
+};
+
+&dc1_prg5 {
+       status = "okay";
+};
+
+&dc1_prg6 {
+       status = "okay";
+};
+
+&dc1_prg7 {
+       status = "okay";
+};
+
+&dc1_prg8 {
+       status = "okay";
+};
+
+&dc1_prg9 {
+       status = "okay";
+};
+
+&dc1_dpr1_channel1 {
+       status = "okay";
+};
+
+&dc1_dpr1_channel2 {
+       status = "okay";
+};
+
+&dc1_dpr1_channel3 {
+       status = "okay";
+};
+
+&dc1_dpr2_channel1 {
+       status = "okay";
+};
+
+&dc1_dpr2_channel2 {
+       status = "okay";
+};
+
+&dc1_dpr2_channel3 {
+       status = "okay";
+};
+
+&dpu2 {
+       status = "okay";
+};
+
 &sai6 {
        assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>,
                        <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,