MLK-16989-3 ARM64: dts: imx8mq: remove unused device nodes

The below legacy fbdev related device nodes are not
used anymore:

   a. dcss
   b. lcdif
   c. mipi_dsi
   d. hdmi

So remove them from IMX8MQ platform to make the dts
more clean.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index a015220..af444fc 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -459,51 +459,6 @@
                clock-names = "ipg";
        };
 
-       dcss: dcss@32e00000 {
-               compatible = "fsl,imx8mq-dcss";
-               reg = <0x0 0x32e00000 0x0 0x25000>,
-                     <0x0 0x32e2f000 0x0 0x1000>;      /* blk_ctl registers */
-               clocks = <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
-                        <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
-                        <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
-                        <&clk IMX8MQ_CLK_DISP_DTRC_DIV>,
-                        <&clk IMX8MQ_CLK_DC_PIXEL_DIV>;
-               clock-names = "axi", "apb", "rtram", "dtrc", "pix";
-               assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>;
-               assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
-               assigned-clock-rates = <594000000>;
-               interrupt-parent = <&irqsteer_dcss>;
-               interrupts = <3 IRQ_TYPE_LEVEL_HIGH>,   /* dpr1 */
-                            <4 IRQ_TYPE_LEVEL_HIGH>,   /* dpr2 */
-                            <5 IRQ_TYPE_LEVEL_HIGH>,   /* dpr3 */
-                            <6 IRQ_TYPE_LEVEL_HIGH>,   /* ctx_ld */
-                            <7 IRQ_TYPE_LEVEL_HIGH>,   /* rd_src */
-                            <8 IRQ_TYPE_LEVEL_HIGH>,   /* dtg_programmable_1: for vsync */
-                            <15 IRQ_TYPE_LEVEL_HIGH>,  /* dec400d_1 */
-                            <16 IRQ_TYPE_LEVEL_HIGH>,  /* dtrc_2 */
-                            <17 IRQ_TYPE_LEVEL_HIGH>,  /* dtrc_3 */
-                            <18 IRQ_TYPE_LEVEL_HIGH>,  /* lut_ld */
-                            <19 IRQ_TYPE_LEVEL_HIGH>;  /* wr_scl */
-               disp-mode = <16>;                       /* <default mode: #16>
-                                                        * #16: 1920x1080p@60Hz 16:9
-                                                        */
-               status = "disabled";
-       };
-
-       lcdif: lcdif@30320000 {
-               compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
-               reg = <0x0 0x30320000 0x0 0x10000>;
-               clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
-                        <&clk IMX8MQ_CLK_DUMMY>,
-                        <&clk IMX8MQ_CLK_DUMMY>;
-               clock-names = "pix", "axi", "disp_axi";
-               assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
-               assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
-               assigned-clock-rate = <594000000>;
-               interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-               status = "disabled";
-       };
-
        csi1_bridge: csi1_bridge@30a90000 {
                compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";
                reg = <0x0 0x30a90000 0x0 0x10000>;
@@ -564,30 +519,6 @@
                status = "disabled";
        };
 
-       mipi_dsi: mipi_dsi@30A00000 {
-               compatible = "fsl,imx8mq-mipi-dsi";
-               reg = <0x0 0x30a00000 0x0 0x10000>;     /* DSI registers */
-               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>,
-                        <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>,
-                        <&clk IMX8MQ_CLK_DSI_DBI_DIV>,
-                        <&clk IMX8MQ_CLK_DSI_AHB_DIV>,
-                        <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
-               clock-names = "core", "phy_ref", "dbi", "rxesc", "txesc";
-               assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
-                                 <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
-                                 <&clk IMX8MQ_CLK_DSI_AHB_SRC>;
-               assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
-                                        <&clk IMX8MQ_SYS1_PLL_266M>,
-                                        <&clk IMX8MQ_SYS1_PLL_80M>;
-               assigned-clock-rate = <594000000>, <266000000>, <80000000>;
-               phy-ref-clkfreq = <27000000>;
-               data-lanes-num = <4>;
-               max-data-rate  = <1500000000>;
-               power-domains = <&mipi_pd>;
-               status = "disabled";
-       };
-
        lcdif_drm: lcdif_drm@30320000 {
                compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
                reg = <0x0 0x30320000 0x0 0x10000>;
@@ -1275,19 +1206,6 @@
                status = "disabled";
        };
 
-       hdmi: hdmi@32c00000 {
-               compatible = "fsl,imx8mq-fb-hdmi";
-               reg = <0x0 0x32c00000 0x0 0x33800>,     /* HDP registers */
-                               <0x0 0x32e40000 0x0 0x40000>;   /* HDP SEC register */
-               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-               video-mode = <16>;      /* <default_mode: #16>
-                                        * #16: 1920x1080p@60HZ 16:9
-                                        * #95: 3840x2160p@30Hz 16:9
-                                        * #97: 3840x2160p@60Hz 16:9
-                                        */
-               status = "disabled";
-       };
-
        hdmi_cec: hdmi_cec@32c33800 {
                compatible = "fsl,imx8-hdp-cec";
                reg = <0x0 0x32c33800 0x0 0x200>;