MLK-15110-17 gpu: imx: dpu: fetchdecode: Add helper fetchdecode_set_burstlength()

This patch adds helper fetchdecode_set_burstlength() so that
the burst length of fetchdecode can be set to appropriate value.
When we don't use prefetch engine, the burst length is set to
the maximal value - 16.  When we use prefetch engine, the burst
length should make the buffer base address align to burst size
but not greater than 16.  This alignment operation can address
the issue recorded by TKT343664.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

diff --git a/drivers/gpu/imx/dpu/dpu-fetchdecode.c b/drivers/gpu/imx/dpu/dpu-fetchdecode.c
index b4ec261..322a991 100644 (file)
--- a/drivers/gpu/imx/dpu/dpu-fetchdecode.c
+++ b/drivers/gpu/imx/dpu/dpu-fetchdecode.c
@@ -217,6 +217,37 @@ void fetchdecode_baddr_autoupdate(struct dpu_fetchdecode *fd, u8 layer_mask)
 }
 EXPORT_SYMBOL_GPL(fetchdecode_baddr_autoupdate);
 
+void fetchdecode_set_burstlength(struct dpu_fetchdecode *fd, dma_addr_t baddr,
+                                bool use_prefetch)
+{
+       struct dpu_soc *dpu = fd->dpu;
+       unsigned int burst_size, burst_length;
+       u32 val;
+
+       if (use_prefetch) {
+               /*
+                * address TKT343664:
+                * fetch unit base address has to align to burst size
+                */
+               burst_size = 1 << (ffs(baddr) - 1);
+               burst_size = min(burst_size, 128U);
+               burst_length = burst_size / 8;
+       } else {
+               burst_length = 16;
+       }
+
+       mutex_lock(&fd->mutex);
+       val = dpu_fd_read(fd, BURSTBUFFERMANAGEMENT);
+       val &= ~SETBURSTLENGTH_MASK;
+       val |= SETBURSTLENGTH(burst_length);
+       dpu_fd_write(fd, val, BURSTBUFFERMANAGEMENT);
+       mutex_unlock(&fd->mutex);
+
+       dev_dbg(dpu->dev, "FetchDecode%d burst length is %u\n",
+                                                       fd->id, burst_length);
+}
+EXPORT_SYMBOL_GPL(fetchdecode_set_burstlength);
+
 void fetchdecode_baseaddress(struct dpu_fetchdecode *fd, dma_addr_t paddr)
 {
        mutex_lock(&fd->mutex);

diff --git a/drivers/gpu/imx/dpu/dpu-prv.h b/drivers/gpu/imx/dpu/dpu-prv.h
index d6111b9..64a5dd8 100644 (file)
--- a/drivers/gpu/imx/dpu/dpu-prv.h
+++ b/drivers/gpu/imx/dpu/dpu-prv.h
@@ -26,6 +26,7 @@
 #define BURSTBUFFERMANAGEMENT          0xC
 #define SETNUMBUFFERS(n)               ((n) & 0xFF)
 #define SETBURSTLENGTH(n)              (((n) & 0x1F) << 8)
+#define SETBURSTLENGTH_MASK            0x1F00
 #define LINEMODE_MASK                  0x80000000U
 #define LINEMODE_SHIFT                 31U
 enum linemode {

diff --git a/include/video/dpu.h b/include/video/dpu.h
index 9ee7427..dd82df2 100644 (file)
--- a/include/video/dpu.h
+++ b/include/video/dpu.h
@@ -472,6 +472,8 @@ int fetchdecode_pixengcfg_dynamic_src_sel(struct dpu_fetchdecode *fd,
                                          fd_dynamic_src_sel_t src);
 void fetchdecode_shden(struct dpu_fetchdecode *fd, bool enable);
 void fetchdecode_baddr_autoupdate(struct dpu_fetchdecode *fd, u8 layer_mask);
+void fetchdecode_set_burstlength(struct dpu_fetchdecode *fd, dma_addr_t baddr,
+                                bool use_prefetch);
 void fetchdecode_baseaddress(struct dpu_fetchdecode *fd, dma_addr_t paddr);
 void fetchdecode_source_bpp(struct dpu_fetchdecode *fd, int bpp);
 void fetchdecode_source_stride(struct dpu_fetchdecode *fd, int stride);