MLK-14438-03 dts: arm64: imx8qm: add enet node

Add enet node for imx8qm.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 212915f..962e305 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -30,6 +30,8 @@
                serial0 = &lpuart0;
                serial1 = &lpuart1;
                mmc0 = &usdhc1;
+               ethernet1 = &fec1;
+               ethernet2 = &fec2;
        };
 
        memory@80000000 {
@@ -1060,12 +1062,38 @@
        };
 
        fec1: ethernet@5b040000 {
-               compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+               compatible = "fsl,imx8qm-fec";
                reg = <0x0 0x5b040000 0x0 0x10000>;
-               interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_TX_CLK>,
+                       <&clk IMX8QM_ENET0_PTP_CLK>;
+               clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+               assigned-clocks = <&clk IMX8QM_ENET0_REF_DIV>, <&clk IMX8QM_ENET0_PTP_CLK>;
+               assigned-clock-rates = <125000000>, <125000000>;
                fsl,num-tx-queues=<3>;
                fsl,num-rx-queues=<3>;
-               fsl,wakeup_irq = <0>;
+               power-domains = <&pd_conn_enet0>;
+               status = "disabled";
+       };
+
+       fec2: ethernet@5b050000 {
+               compatible = "fsl,imx8qm-fec";
+               reg = <0x0 0x5b050000 0x0 0x10000>;
+               interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_TX_CLK>,
+                       <&clk IMX8QM_ENET1_PTP_CLK>;
+               clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+               assigned-clocks = <&clk IMX8QM_ENET1_REF_DIV>, <&clk IMX8QM_ENET1_PTP_CLK>;
+               assigned-clock-rates = <125000000>, <125000000>;
+               fsl,num-tx-queues=<3>;
+               fsl,num-rx-queues=<3>;
+               power-domains = <&pd_conn_enet1>;
                status = "disabled";
        };