MLK-14675: ARM: dts: set pll4 rate for audio

There is noise when use ssi master mode. the reason is the ssi rate
is not accurate for ssi master mode, show below.

    pll3_pfd2_508m               0            0   508235294          0 0
       ssi3_sel                  0            0   508235294          0 0
          ssi3_pred              0            0   127058824          0 0
             ssi3_podf           0            0    63529412          0 0
                ssi3             0            0    63529412          0 0
       ssi2_sel                  0            0   508235294          0 0
          ssi2_pred              0            0   127058824          0 0
             ssi2_podf           0            0    63529412          0 0
                ssi2             0            0    63529412          0 0

so we need to switch ssi's parent to pll4 (which is dedicate audio pll),
and set a proper rate for pll4, we select 786432000Hz, which can
generate 32kHz,48kHz,96KHz.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>

diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 61c8716..04e0d2b 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -999,6 +999,13 @@
 };
 
 &ssi2 {
+       assigned-clocks = <&clks IMX6QDL_CLK_PLL4>,
+                         <&clks IMX6QDL_PLL4_BYPASS>,
+                         <&clks IMX6QDL_CLK_SSI2_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>,
+                                <&clks IMX6QDL_CLK_PLL4>,
+                                <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+       assigned-clock-rates = <786432000>, <0>, <0>;
        status = "okay";
 };