MLK-16926-4: arm64: dts: fsl-imx8mq-evk: Add sync polarity for LCDIF use-cases

For some reasons, the sync polarity of the eLCDIF when used with NWL DSI
controller needs to be HIGH, so set it in the DTS nodes.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts
index 4739883..133ace3 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-adv7535.dts
@@ -72,6 +72,7 @@
 &mipi_dsi {
        status = "okay";
        as_bridge;
+       sync-pol = <1>;
 
        port@1 {
                mipi_dsi_in: endpoint {

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts
index 72c7530..884cdad 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dts
@@ -62,6 +62,7 @@
 &mipi_dsi {
        status = "okay";
        as_bridge;
+       sync-pol = <1>;
        assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
                          <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
                          <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,