MLK-15046-9 arm64: dts: imx8qm: add flexcan support

Add flexcan 1, 2 ,3 support.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index 0dd4b3b..3e632d0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -55,6 +55,25 @@
                        regulator-max-microvolt = <3300000>;
                        regulator-always-on;
                };
+
+               reg_can_en: regulator-can-gen {
+                       compatible = "regulator-fixed";
+                       regulator-name = "can-en";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&pca9557_b 5 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_can_stby: regulator-can-stby {
+                       compatible = "regulator-fixed";
+                       regulator-name = "can-stby";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&pca9557_b 4 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       vin-supply = <&reg_can_en>;
+               };
        };
 
        sound-cs42888 {
@@ -265,6 +284,27 @@
                        >;
                };
 
+               pinctrl_flexcan1: flexcan0grp {
+                       fsl,pins = <
+                               SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX        0x21
+                               SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX        0x21
+                       >;
+               };
+
+               pinctrl_flexcan2: flexcan1grp {
+                       fsl,pins = <
+                               SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX        0x21
+                               SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX        0x21
+                       >;
+               };
+
+               pinctrl_flexcan3: flexcan2grp {
+                       fsl,pins = <
+                               SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX        0x21
+                               SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX        0x21
+                       >;
+               };
+
                pinctrl_flexspi0: flexspi0grp {
                        fsl,pins = <
                                SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x0600004c
@@ -389,6 +429,27 @@
        status = "disabled";
 };
 
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       xceiver-supply = <&reg_can_stby>;
+       status = "okay";
+};
+
+&flexcan2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       xceiver-supply = <&reg_can_stby>;
+       status = "okay";
+};
+
+&flexcan3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan3>;
+       xceiver-supply = <&reg_can_stby>;
+       status = "okay";
+};
+
 &flexspi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexspi0>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 6e66ad9..aba19ad 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -975,6 +975,45 @@
                power-domains = <&pd_lvds0>;
        };
 
+       flexcan1: can@5a8d0000 {
+               compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
+               reg = <0x0 0x5a8d0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QM_CAN0_IPG_CLK>,
+                        <&clk IMX8QM_CAN0_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QM_CAN0_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_flexcan0>;
+               status = "disabled";
+       };
+
+       flexcan2: can@5a8e0000 {
+               compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
+               reg = <0x0 0x5a8e0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QM_CAN1_IPG_CLK>,
+                        <&clk IMX8QM_CAN1_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QM_CAN1_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_flexcan1>;
+               status = "disabled";
+       };
+
+       flexcan3: can@5a8f0000 {
+               compatible = "fsl,imx8qm-flexcan", "fsl,imx6q-flexcan";
+               reg = <0x0 0x5a8f0000 0x0 0x10000>;
+               interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8QM_CAN2_IPG_CLK>,
+                        <&clk IMX8QM_CAN2_CLK>;
+               clock-names = "ipg", "per";
+               assigned-clocks = <&clk IMX8QM_CAN2_CLK>;
+               assigned-clock-rates = <24000000>;
+               power-domains = <&pd_dma_flexcan2>;
+               status = "disabled";
+       };
+
        i2c1_lvds0: i2c@56247000 {
                compatible = "fsl,imx8qm-lpi2c";
                reg = <0x0 0x56247000 0x0 0x1000>;