/*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ENET0 MDIO are shared */
#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
/* MAX7322 */
#ifdef CONFIG_FEC_ENABLE_MAX7322
#define CONFIG_MAX7322_I2C_ADDR 0x68
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ENET0 MDIO are shared */
#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ENET0 MDIO are shared */
#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
/* MAX7322 */
#ifdef CONFIG_FEC_ENABLE_MAX7322
#define CONFIG_MAX7322_I2C_ADDR 0x68
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ENET0 MDIO are shared */
#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \