arm64: dts: imx8mn-somdevices.dtsi: Configure WiFi/BT pins.

Signed-off-by: Josep Orga <jorga@somdevices.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi
index c9b0403..c6c6e72 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-somdevices.dtsi
@@ -34,7 +34,7 @@
 
        modem_reset: modem-reset {
                compatible = "gpio-reset";
-               reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
                reset-delay-us = <2000>;
                reset-post-delay-ms = <40>;
                #reset-cells = <0>;
@@ -44,7 +44,8 @@
                compatible = "mmc-pwrseq-simple";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_usdhc1_gpio>;
-               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>,
+                             <&gpio2 6 GPIO_ACTIVE_LOW>;
        };
 
        reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -521,11 +522,11 @@
 
        pinctrl_uart1: uart1grp {
                fsl,pins = <
-                       MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
-                       MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
-                       MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
-                       MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
-                       MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
+                       MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B  0x140
+                       MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX     0x140
+                       MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX      0x140
+                       MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B  0x140
+                       MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
                >;
        };
 
@@ -548,6 +549,7 @@
        pinctrl_usdhc1_gpio: usdhc1grpgpio {
                fsl,pins = <
                        MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
+                       MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
                >;
        };