MLK-14952 arm64: dts: imx8qm/qxp: add enet support

Add enet support for i.MX8QM and i.MX8QXP lpddr4 arm2 board.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index be3a4fc..fdc05bf 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -63,6 +63,25 @@
                        >;
                };
 
+               pinctrl_fec2: fec2grp {
+                       fsl,pins = <
+                               SC_P_ENET1_MDC_CONN_ENET1_MDC                   0x06000048
+                               SC_P_ENET1_MDIO_CONN_ENET1_MDIO                 0x06000048
+                               SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048
+                               SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC       0x06000048
+                               SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0     0x06000048
+                               SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1     0x06000048
+                               SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2     0x06000048
+                               SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3     0x06000048
+                               SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC       0x06000048
+                               SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048
+                               SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0     0x06000048
+                               SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1     0x06000048
+                               SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2     0x06000048
+                               SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3     0x06000048
+                       >;
+               };
+
                pinctrl_lpuart0: lpuart0grp {
                        fsl,pins = <
                                SC_P_UART0_RX_DMA_UART0_RX              0x0600004c
@@ -214,9 +233,24 @@
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
                };
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
        };
 };
 
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec2>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy1>;
+       fsl,ar8031-phy-fixup;
+       fsl,magic-packet;
+       status = "disabled";
+};
+
 &flexspi0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexspi0>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index ff7040b..686bbe7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -29,13 +29,13 @@
        #size-cells = <2>;
 
        aliases {
+               ethernet1 = &fec1;
+               ethernet2 = &fec2;
                serial0 = &lpuart0;
                serial1 = &lpuart1;
                mmc0 = &usdhc1;
                mmc1 = &usdhc2;
                mmc2 = &usdhc3;
-               ethernet1 = &fec1;
-               ethernet2 = &fec2;
                usbphy0 = &usbphy1;
        };
 
@@ -1285,7 +1285,7 @@
                                <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_TX_CLK>,
+               clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
                        <&clk IMX8QM_ENET0_PTP_CLK>;
                clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
                assigned-clocks = <&clk IMX8QM_ENET0_REF_DIV>, <&clk IMX8QM_ENET0_PTP_CLK>;
@@ -1303,7 +1303,7 @@
                                <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_TX_CLK>,
+               clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
                        <&clk IMX8QM_ENET1_PTP_CLK>;
                clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
                assigned-clocks = <&clk IMX8QM_ENET1_REF_DIV>, <&clk IMX8QM_ENET1_PTP_CLK>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index 4719693..3d34529 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -46,6 +46,42 @@
 &iomuxc {
        imx8qxp-lpddr4-arm2 {
 
+               pinctrl_fec1: fec1grp {
+                       fsl,pins = <
+                               SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000048
+                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000048
+                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
+                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x06000048
+                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x06000048
+                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x06000048
+                               SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x06000048
+                               SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x06000048
+                               SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x06000048
+                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
+                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x06000048
+                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x06000048
+                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x06000048
+                               SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x06000048
+                       >;
+               };
+
+               pinctrl_fec2: fec2grp {
+                       fsl,pins = <
+                               SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x06000048
+                               SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC             0x06000048
+                               SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x06000048
+                               SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x06000048
+                               SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2            0x06000048
+                               SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3           0x06000048
+                               SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC             0x06000048
+                               SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x06000048
+                               SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x06000048
+                               SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x06000048
+                               SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2        0x06000048
+                               SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3            0x06000048
+                       >;
+               };
+
                pinctrl_lpi2c1: lpi1cgrp {
                        fsl,pins = <
                                SC_P_USB_SS3_TC0_ADMA_I2C1_SCL  0x06000020
@@ -105,6 +141,41 @@
        };
 };
 
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy0>;
+       fsl,ar8031-phy-fixup;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec2>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy1>;
+       fsl,ar8031-phy-fixup;
+       fsl,magic-packet;
+       status = "disabled";
+};
+
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 4777f41..4786d14 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -28,6 +28,8 @@
        #size-cells = <2>;
 
        aliases {
+               ethernet0 = &fec1;
+               ethernet1 = &fec2;
                serial0 = &lpuart0;
                mmc0 = &usdhc1;
                mmc1 = &usdhc2;
@@ -942,7 +944,7 @@
                                <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>,
+               clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
                        <&clk IMX8QXP_ENET0_PTP_CLK>;
                clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
                assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
@@ -960,7 +962,7 @@
                                <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
                                <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>,
+               clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>,
                        <&clk IMX8QXP_ENET1_PTP_CLK>;
                clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
                assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;