#include <asm/arch/clock.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/imx8-pins.h>
+#include <usb.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
+#include "../common/tcpc.h"
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
- (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
- (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
- (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+ | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+ | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+
+#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+ | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+
+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+ | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
static iomux_cfg_t uart0_pads[] = {
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
setup_iomux_uart();
- sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
-
return 0;
}
-#if CONFIG_IS_ENABLED(DM_GPIO)
-static void board_gpio_init(void)
-{
- /* TODO */
-}
-#else
-static inline void board_gpio_init(void) {}
-#endif
#if IS_ENABLED(CONFIG_FEC_MXC)
#include <miiphy.h>
+#ifndef CONFIG_DM_ETH
+static iomux_cfg_t pad_enet1[] = {
+ SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+ /* Shared MDIO */
+ SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static iomux_cfg_t pad_enet0[] = {
+ SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+ SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+ /* Shared MDIO */
+ SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ if (0 == CONFIG_FEC_ENET_DEV)
+ imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+ else
+ imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ struct power_domain pd;
+
+ printf("[%s] %d\n", __func__, __LINE__);
+
+ if (CONFIG_FEC_ENET_DEV) {
+ if (!power_domain_lookup_name("conn_enet1", &pd))
+ power_domain_on(&pd);
+ } else {
+ if (!power_domain_lookup_name("conn_enet0", &pd))
+ power_domain_on(&pd);
+ }
+
+ setup_iomux_fec();
+
+ ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+ CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+ if (ret)
+ printf("FEC1 MXC: %s:failed\n", __func__);
+
+ return ret;
+}
+
int board_phy_config(struct phy_device *phydev)
{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
return 0;
}
#endif
+#endif
+
+#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
+#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
+#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
+
+static void board_gpio_init(void)
+{
+ int ret;
+ struct gpio_desc desc;
+
+ ret = dm_gpio_lookup_name("GPIO4_20", &desc);
+ if (ret) {
+ printf("%s lookup GPIO@4_20 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&desc, "bb_3v3_1");
+ if (ret) {
+ printf("%s request bb_3v3_1 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ ret = dm_gpio_lookup_name("GPIO4_24", &desc);
+ if (ret) {
+ printf("%s lookup GPIO@4_24 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&desc, "bb_3v3_2");
+ if (ret) {
+ printf("%s request bb_3v3_2 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ ret = dm_gpio_lookup_name("GPIO4_23", &desc);
+ if (ret) {
+ printf("%s lookup GPIO@4_23 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&desc, "bb_3v3_3");
+ if (ret) {
+ printf("%s request bb_3v3_3 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
int checkboard(void)
{
puts("Board: iMX8QM MEK\n");
return 0;
}
-int board_init(void)
+#ifdef CONFIG_USB
+
+#ifdef CONFIG_USB_TCPC
+struct gpio_desc type_sel_desc;
+
+static iomux_cfg_t ss_mux_gpio[] = {
+ SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+ SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+ .i2c_bus = 0,
+ .addr = 0x51,
+ .port_type = TYPEC_PORT_DFP,
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+ if (pol == TYPEC_POLARITY_CC1)
+ dm_gpio_set_value(&type_sel_desc, 0);
+ else
+ dm_gpio_set_value(&type_sel_desc, 1);
+}
+
+static void setup_typec(void)
+{
+ int ret;
+ struct gpio_desc typec_en_desc;
+
+ imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+ ret = dm_gpio_lookup_name("GPIO4_6", &type_sel_desc);
+ if (ret) {
+ printf("%s lookup GPIO4_6 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&type_sel_desc, "typec_sel");
+ if (ret) {
+ printf("%s request typec_sel failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
+
+ ret = dm_gpio_lookup_name("GPIO4_19", &typec_en_desc);
+ if (ret) {
+ printf("%s lookup GPIO4_19 failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ ret = dm_gpio_request(&typec_en_desc, "typec_en");
+ if (ret) {
+ printf("%s request typec_en failed ret = %d\n", __func__, ret);
+ return;
+ }
+
+ /* Enable SS MUX */
+ dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ tcpc_init(&port, port_config, &ss_mux_select);
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret = 0;
+
+ if (index == 1) {
+ if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+ ret = tcpc_setup_dfp_mode(&port);
+#endif
+#ifdef CONFIG_USB_CDNS3_GADGET
+ } else {
+#ifdef CONFIG_USB_TCPC
+ ret = tcpc_setup_ufp_mode(&port);
+ printf("%d setufp mode %d\n", index, ret);
+#endif
+#endif
+ }
+ }
+
+ return ret;
+
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
{
- /* Power up base board */
- sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
+ int ret = 0;
+ if (index == 1) {
+ if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+ ret = tcpc_disable_src_vbus(&port);
+#endif
+ }
+ }
+
+ return ret;
+}
+#endif
+
+int board_init(void)
+{
board_gpio_init();
+
+#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC)
+ setup_typec();
+#endif
+
return 0;
}
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x100000
CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
CONFIG_TARGET_IMX8QM_MEK=y
CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
#include "imx_env.h"
#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SPL_MAX_SIZE (192 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
-#define CONFIG_SPL_STACK 0x013E000
-#define CONFIG_SPL_BSS_START_ADDR 0x00128000
+#define CONFIG_SPL_STACK 0x013fff0
+#define CONFIG_SPL_BSS_START_ADDR 0x00130000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x82200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
-#define CONFIG_MALLOC_F_ADDR 0x00120000
+#define CONFIG_MALLOC_F_ADDR 0x00138000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
-#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define FEC_QUIRK_ENET_MAC
+
+/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
+#define CONFIG_FEC_ENET_DEV 0
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE 0x5B040000
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_ETHPRIME "eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE 0x5B050000
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+#define CONFIG_ETHPRIME "eth1"
+#endif
+
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
#define AHAB_ENV "sec_boot=no\0"
#endif
+/* Boot M4 */
+#define M4_BOOT_ENV \
+ "m4_0_image=m4_0.bin\0" \
+ "m4_1_image=m4_1.bin\0" \
+ "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+ "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
+ "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+ "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
#define CONFIG_MFG_ENV_SETTINGS \
CONFIG_MFG_ENV_SETTINGS_DEFAULT \
"initrd_addr=0x83100000\0" \
"initrd_high=0xffffffffffffffff\0" \
"emmc_dev=0\0" \
- "sd_dev=1\0" \
+ "sd_dev=1\0"
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_MFG_ENV_SETTINGS \
+ M4_BOOT_ENV \
AHAB_ENV \
"script=boot.scr\0" \
"image=Image\0" \
"panel=NULL\0" \
- "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
+ "console=ttyLP0\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"echo wait for boot; " \
"fi;" \
"fi;\0" \
- "netargs=setenv bootargs console=${console} " \
+ "netargs=setenv bootargs console=${console},${baudrate} earlycon " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "booti ${loadaddr} - ${fdt_addr}; " \
+ "run boot_os; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
-/* Default environment is in SD */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
-/* Networking */
-#define CONFIG_FEC_XCV_TYPE RGMII
+/* Serial */
+#define CONFIG_BAUDRATE 115200
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SERIAL_TAG
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USBD_HS
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
#endif /* __IMX8QM_MEK_H */
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