drm/amdgpu: assign the doorbell index to mes ring
authorJack Xiao <Jack.Xiao@amd.com>
Fri, 26 Apr 2019 10:58:41 +0000 (18:58 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:07 +0000 (01:59 -0400)
MES ring will use the assigned doorbell index for
command submission.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
drivers/gpu/drm/amd/amdgpu/nv.c

index 821289b..89e6ad3 100644 (file)
@@ -53,6 +53,7 @@ struct amdgpu_doorbell_index {
        uint32_t gfx_ring0;
        uint32_t gfx_ring1;
        uint32_t sdma_engine[8];
+       uint32_t mes_ring;
        uint32_t ih;
        union {
                struct {
@@ -177,6 +178,7 @@ typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
        AMDGPU_NAVI10_DOORBELL_USERQUEUE_END            = 0x08A,
        AMDGPU_NAVI10_DOORBELL_GFX_RING0                = 0x08B,
        AMDGPU_NAVI10_DOORBELL_GFX_RING1                = 0x08C,
+       AMDGPU_NAVI10_DOORBELL_MES_RING                 = 0x090,
        /* SDMA:256~335*/
        AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0             = 0x100,
        AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1             = 0x10A,
index b4178ce..cad66cb 100644 (file)
@@ -573,6 +573,7 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
        adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
        adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
        adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
+       adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
        adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
        adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
        adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;