MLK-22589 imx8: Enable lpcg for some clocks

Have missed the lpcg settings when porting to 2019.04 u-boot

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 4096d7806a0dcc501123c8c2cdf734620e37d169)

diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 283b648..97503d7 100644 (file)
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -33,6 +33,7 @@
 #include <asm/mach-imx/imx_vservice.h>
 #include <asm/arch/power-domain.h>
 #include <spl.h>
+#include <asm/arch/lpcg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -280,6 +281,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
                        return -EIO;
                }
 
+               lpcg_all_clock_on(AUD_DSP_LPCG);
+
                if (!power_domain_lookup_name("audio_sai0", &pd)) {
                        if (power_domain_on(&pd)) {
                                printf("Error power on SAI0\n");
@@ -293,6 +296,9 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
                                return -EIO;
                        }
                }
+
+               lpcg_all_clock_on(AUD_OCRAM_LPCG);
+               lpcg_all_clock_on(AUD_SAI_0_LPCG);
        }
 
        printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);

diff --git a/arch/arm/mach-imx/imx8/video_common.c b/arch/arm/mach-imx/imx8/video_common.c
index 97ce908..6157f80 100644 (file)
--- a/arch/arm/mach-imx/imx8/video_common.c
+++ b/arch/arm/mach-imx/imx8/video_common.c
@@ -22,6 +22,7 @@
 #include <asm/arch/imx8_mipi_dsi.h>
 #include <asm/arch/video_common.h>
 #include <power-domain.h>
+#include <asm/arch/lpcg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -340,6 +341,7 @@ int display_controller_setup(sc_pm_clock_rate_t pixel_clock)
        sc_rsrc_t dc_rsrc, pll0_rsrc, pll1_rsrc;
        sc_pm_clock_rate_t pll_clk;
        const char *pll1_pd_name;
+       u32 dc_lpcg;
 
        int dc_id = gdc;
 
@@ -351,11 +353,13 @@ int display_controller_setup(sc_pm_clock_rate_t pixel_clock)
                pll0_rsrc = SC_R_DC_0_PLL_0;
                pll1_rsrc = SC_R_DC_0_PLL_1;
                pll1_pd_name = "dc0_pll1";
+               dc_lpcg = DC_0_LPCG;
        } else {
                dc_rsrc = SC_R_DC_1;
                pll0_rsrc = SC_R_DC_1_PLL_0;
                pll1_rsrc = SC_R_DC_1_PLL_1;
                pll1_pd_name = "dc1_pll1";
+               dc_lpcg = DC_1_LPCG;
        }
 
        if (!power_domain_lookup_name(pll1_pd_name, &pd)) {
@@ -423,6 +427,8 @@ int display_controller_setup(sc_pm_clock_rate_t pixel_clock)
                return -EIO;
        }
 
+       lpcg_all_clock_on(dc_lpcg);
+
        err = sc_misc_set_control(-1, dc_rsrc, SC_C_PXL_LINK_MST1_ADDR, 0);
        if (err != SC_ERR_NONE) {
                printf("DC Set control fSC_C_PXL_LINK_MST1_ADDR ailed! (error = %d)\n", err);