MLK-25446-5: arm64: dts: imx8mp-evk: enable usdhc1 bus on M.2 interface

The patch is to enable usdhc1 on M.2 interface for SDIO wlan, and need
to disable PCIE interface on M.2.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 7a5fb40..49149ff 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -85,7 +85,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-rm67191.dtb imx8mp-evk-it626
                          imx8mp-evk-ov2775-ov5640.dtb imx8mp-evk-basler-ov5640.dtb imx8mp-evk-basler.dtb \
                          imx8mp-evk-dual-ov2775.dtb imx8mp-evk-spdif-lb.dtb imx8mp-evk-dsp.dtb \
                          imx8mp-evk-dsp-lpa.dtb imx8mp-evk-sof-wm8960.dtb \
-                         imx8mp-evk-iqaudio-dacplus.dtb imx8mp-evk-iqaudio-dacpro.dtb imx8mp-evk-hifiberry-dacplus.dtb
+                         imx8mp-evk-iqaudio-dacplus.dtb imx8mp-evk-iqaudio-dacpro.dtb imx8mp-evk-hifiberry-dacplus.dtb \
+                         imx8mp-evk-usdhc1-m2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mp-ab2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts
new file mode 100644 (file)
index 0000000..d495567
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-usdhc1-m2.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+#include "imx8mp-evk.dts"
+
+/ {
+       usdhc1_pwrseq: usdhc1_pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+       };
+};
+
+&iomuxc {
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x190
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d0
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d0
+                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x19
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09      0x1c4
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x194
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d4
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d4
+                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x19
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09      0x1c4
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x196
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d6
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d6
+                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x19
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09      0x1c4
+               >;
+       };
+};
+
+&pcie {
+       status = "disabled";
+       /delete-node/ wifi_wake_host;
+};
+
+&pcie_phy {
+       status = "disabled";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       keep-power-in-suspend;
+       non-removable;
+       mmc-pwrseq = <&usdhc1_pwrseq>;
+       status = "okay";
+
+       wifi_wake_host {
+               compatible = "nxp,wifi-wake-host";
+               interrupt-parent = <&gpio2>;
+               interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "host-wake";
+       };
+};