MLK-12425-6: mx7: add epdc qos settings

This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.

Signed-off-by: Robby Cai <r63905@freescale.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 1b32518d1c27f05eb84a4cb93594710354b2e343)
(cherry picked from commit 8fd2dbe9097b09715f84e1c0c17dcd6a6351fb35)
(cherry picked from commit a92a02f984aa7871aa5bb1a83e0e3f444796fedd)
(cherry picked from commit 682b705b402827f6041839d92a717887a2a9649d)
(cherry picked from commit 4c50797b34115c2f40552329fb4901d588e6bef9)

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 50b27b6..7e830c4 100644 (file)
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -212,6 +212,10 @@
 #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
 #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
 #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
+#define REGS_QOS_BASE     QOSC_IPS_BASE_ADDR
+#define REGS_QOS_EPDC     (QOSC_IPS_BASE_ADDR + 0x3400)
+#define REGS_QOS_PXP0     (QOSC_IPS_BASE_ADDR + 0x2C00)
+#define REGS_QOS_PXP1     (QOSC_IPS_BASE_ADDR + 0x3C00)
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR     0x68

diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 9a66f33..19e11e5 100644 (file)
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -309,6 +309,30 @@ static void imx_gpcv2_init(void)
        udelay(65);
 }
 
+static void set_epdc_qos(void)
+{
+       writel(0, REGS_QOS_BASE);  /*  Disable clkgate & soft_reset */
+       writel(0, REGS_QOS_BASE + 0x60);  /*  Enable all masters */
+       writel(0, REGS_QOS_EPDC);   /*  Disable clkgate & soft_reset */
+       writel(0, REGS_QOS_PXP0);   /*  Disable clkgate & soft_reset */
+       writel(0, REGS_QOS_PXP1);   /*  Disable clkgate & soft_reset */
+
+       writel(0x0f020722, REGS_QOS_EPDC + 0xd0);   /*  WR, init = 7 with red flag */
+       writel(0x0f020722, REGS_QOS_EPDC + 0xe0);   /*  RD,  init = 7 with red flag */
+
+       writel(1, REGS_QOS_PXP0);   /*  OT_CTRL_EN =1 */
+       writel(1, REGS_QOS_PXP1);   /*  OT_CTRL_EN =1 */
+
+       writel(0x0f020222, REGS_QOS_PXP0 + 0x50);   /*  WR,  init = 2 with red flag */
+       writel(0x0f020222, REGS_QOS_PXP1 + 0x50);   /*  WR,  init = 2 with red flag */
+       writel(0x0f020222, REGS_QOS_PXP0 + 0x60);   /*  rD,  init = 2 with red flag */
+       writel(0x0f020222, REGS_QOS_PXP1 + 0x60);   /*  rD,  init = 2 with red flag */
+       writel(0x0f020422, REGS_QOS_PXP0 + 0x70);   /*  tOTAL,  init = 4 with red flag */
+       writel(0x0f020422, REGS_QOS_PXP1 + 0x70);   /*  TOTAL,  init = 4 with red flag */
+
+       writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */
+}
+
 int arch_cpu_init(void)
 {
        init_aips();
@@ -319,6 +343,8 @@ int arch_cpu_init(void)
 
        init_cpu_basic();
 
+       set_epdc_qos();
+
 #if CONFIG_IS_ENABLED(IMX_RDC)
        isolate_resource();
 #endif