u64 caam_id;
struct device *dev;
struct device_node *nprop, *np;
+ struct resource res_regs;
struct caam_ctrl __iomem *ctrl;
struct caam_drv_private *ctrlpriv;
u32 comp_params;
goto disable_clocks;
}
- ctrlpriv->sm_base = of_iomap(np, 0);
+ /* Get CAAM SM registers base address from device tree */
+ ret = of_address_to_resource(np, 0, &res_regs);
+ if (ret) {
+ dev_err(dev, "failed to retrieve registers base from device tree\n");
+ ret = -ENODEV;
+ goto disable_clocks;
+ }
+
+ ctrlpriv->sm_phy = res_regs.start;
+ ctrlpriv->sm_base = devm_ioremap_resource(dev, &res_regs);
+ if (IS_ERR(ctrlpriv->sm_base)) {
+ ret = PTR_ERR(ctrlpriv->sm_base);
+ goto disable_clocks;
+ }
+
if (!of_machine_is_compatible("fsl,imx8mq") &&
!of_machine_is_compatible("fsl,imx8qm") &&
!of_machine_is_compatible("fsl,imx8qxp"))
- ctrlpriv->sm_size = 0x3fff;
+ ctrlpriv->sm_size = resource_size(&res_regs);
else
ctrlpriv->sm_size = PG_SIZE_64K;
/* JobR's register space */
struct caam_job_ring __iomem *jr[JOBR_MAX_COUNT];
dma_addr_t __iomem *sm_base; /* Secure memory storage base */
+ phys_addr_t sm_phy; /* Secure memory storage physical */
u32 sm_size;
/*
lpagedesc[page].pg_phys = (u8 *)0x20800000 +
(smpriv->page_size * page);
} else {
-/* FIXME: get base address from platform property... */
- lpagedesc[page].pg_phys = (u8 *)0x00100000 +
+ lpagedesc[page].pg_phys =
+ (u8 *) ctrlpriv->sm_phy +
(smpriv->page_size * page);
}
lpagect++;