MLK-13497 clock: make an accurate pixel cock rate for epdc on i.mx6sll

change parent clock to pll3_pfd2 and calculate out a desired pixel clock
rate. This patch fixed the following warning.
"imx_epdc_v2_fb 20f4000.epdc: Unable to get an accurate EPDC pix clkdesired = 40000000, actual = 63529412"

Signed-off-by: Robby Cai <robby.cai@nxp.com>

diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c
index cd16c2d..296440f 100644 (file)
--- a/drivers/clk/imx/clk-imx6sll.c
+++ b/drivers/clk/imx/clk-imx6sll.c
@@ -366,6 +366,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
        imx_clk_set_parent(clks[IMX6SLL_CLK_PERIPH], clks[IMX6SLL_CLK_PERIPH_PRE]);
 
        imx_clk_set_rate(clks[IMX6SLL_CLK_AHB], 132000000);
+
+       /* Configure EPDC clocks */
+       imx_clk_set_rate(clks[IMX6SLL_CLK_PLL3_PFD2], 320000000);
+       clk_set_parent(clks[IMX6SLL_CLK_EPDC_PRE_SEL],
+               clks[IMX6SLL_CLK_PLL3_PFD2]);
+
 }
 
 CLK_OF_DECLARE(imx6sll, "fsl,imx6sll-ccm", imx6sll_clocks_init);