MLK-16738: ASoC: fsl: amix: move SAIs MCLKs to AUD_PLL1

Move AMIX SAIs MCLKs to AUD_PLL1 and double the frequency
in order to support 64k rate.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index 3685f4a..a6664c2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -166,12 +166,12 @@
 
 &sai6 {
        assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>,
-                       <&clk IMX8QM_AUD_PLL0_DIV>,
-                       <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
-                       <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
+                       <&clk IMX8QM_AUD_PLL1_DIV>,
+                       <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
+                       <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
                        <&clk IMX8QM_AUD_SAI_6_MCLK>;
-       assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
-       assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
+       assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
+       assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
        fsl,sai-asynchronous;
        fsl,txm-rxs;
        status = "okay";
@@ -179,12 +179,12 @@
 
 &sai7 {
        assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>,
-                       <&clk IMX8QM_AUD_PLL0_DIV>,
-                       <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
-                       <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
+                       <&clk IMX8QM_AUD_PLL1_DIV>,
+                       <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
+                       <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
                        <&clk IMX8QM_AUD_SAI_7_MCLK>;
-       assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
-       assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
+       assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
+       assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
        fsl,sai-asynchronous;
        fsl,txm-rxs;
        status = "okay";