MLK-16669: arm64: dts: access nor chip via lpspi on i.MX8QXP ARM2 base board

To access the nor chip on i.MX8QXP ARM2 base board, enable the lpspi in
device tree, the gpio_cs is also needed.

BuildInfo:
- SCFW 9e9f6ec6, IMX-MKIMAGE e1b3bc76, ATF 0
- U-Boot 2017.03-00072-gfdcf70a

Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
index d97a118..bf87f19 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
@@ -225,6 +225,21 @@
                        >;
                };
 
+               pinctrl_lpspi0: lpspi0grp {
+                       fsl,pins = <
+                               SC_P_SPI0_SCK_ADMA_SPI0_SCK             0x0600004c
+                               SC_P_SPI0_SDO_ADMA_SPI0_SDO             0x0600004c
+                               SC_P_SPI0_SDI_ADMA_SPI0_SDI             0x0600004c
+                               SC_P_SPI0_CS1_ADMA_SPI0_CS1             0x0600004c
+                       >;
+               };
+
+               pinctrl_lpspi0_cs: lpspi0cs {
+                       fsl,pins = <
+                               SC_P_SPI0_CS0_LSIO_GPIO1_IO08           0x21
+                       >;
+               };
+
                pinctrl_flexcan1: flexcan0grp {
                        fsl,pins = <
                                SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX               0x21
@@ -628,6 +643,24 @@
        };
 };
 
+&lpspi0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       fsl,spi-num-chipselects = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
+       cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+       status = "okay";
+
+       flash: at45db041e@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "atmel,at45", "atmel,dataflash";
+               spi-max-frequency = <500000>;
+               reg = <0>;
+        };
+};
+
 &lpuart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_lpuart0>;

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 8ca506f..0e47d45 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -1569,6 +1569,20 @@
                interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
        };
 
+       lpspi0: lpspi@5a000000 {
+               compatible = "fsl,imx7ulp-spi";
+               reg = <0x0 0x5a000000 0x0 0x10000>;
+               interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-parent = <&gic>;
+               clocks = <&clk IMX8QXP_SPI0_CLK>,
+                        <&clk IMX8QXP_SPI0_IPG_CLK>;
+               clock-names = "per", "ipg";
+               assigned-clocks = <&clk IMX8QXP_SPI0_CLK>;
+               assigned-clock-rates = <20000000>;
+               power-domains = <&pd_dma_lpspi0>;
+               status = "disabled";
+       };
+
        lpuart0: serial@5a060000 {
                compatible = "fsl,imx8qm-lpuart";
                reg = <0x0 0x5a060000 0x0 0x1000>;