scsi: ufs-qcom: Delay specific time before gate ref clk
authorCan Guo <cang@codeaurora.org>
Tue, 11 Feb 2020 03:40:50 +0000 (19:40 -0800)
committerMartin K. Petersen <martin.petersen@oracle.com>
Thu, 13 Feb 2020 00:42:38 +0000 (19:42 -0500)
After enter hibern8, as UFS JEDEC ver 3.0 requires, a specific gating wait
time is required before disable the device reference clock. If it is not
specified, use the old delay.

Link: https://lore.kernel.org/r/1581392451-28743-8-git-send-email-cang@codeaurora.org
Reviewed-by: Asutosh Das <asutoshd@codeaurora.org>
Reviewed-by: Hongwu Su <hongwus@codeaurora.org>
Signed-off-by: Can Guo <cang@codeaurora.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
drivers/scsi/ufs/ufs-qcom.c

index 2800a47..8339050 100644 (file)
@@ -843,11 +843,27 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
                /*
                 * If we are here to disable this clock it might be immediately
                 * after entering into hibern8 in which case we need to make
-                * sure that device ref_clk is active at least 1us after the
+                * sure that device ref_clk is active for specific time after
                 * hibern8 enter.
                 */
-               if (!enable)
-                       udelay(1);
+               if (!enable) {
+                       unsigned long gating_wait;
+
+                       gating_wait = host->hba->dev_info.clk_gating_wait_us;
+                       if (!gating_wait) {
+                               udelay(1);
+                       } else {
+                               /*
+                                * bRefClkGatingWaitTime defines the minimum
+                                * time for which the reference clock is
+                                * required by device during transition from
+                                * HS-MODE to LS-MODE or HIBERN8 state. Give it
+                                * more delay to be on the safe side.
+                                */
+                               gating_wait += 10;
+                               usleep_range(gating_wait, gating_wait + 10);
+                       }
+               }
 
                writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);