MLK-23303-1 dts: arm64: add the pcie support on imx8mp

Add the PCIe support on iMX8MP.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <Fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 6a6f649..b611a1b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -598,6 +598,28 @@
        status = "okay";
 };
 
+&pcie{
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
+       reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
+       ext_osc = <0>;
+       clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
+                <&clk IMX8MP_CLK_PCIE_AUX>,
+                <&clk IMX8MP_CLK_PCIE_PHY>,
+                <&clk IMX8MP_CLK_PCIE_ROOT>;
+       clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+       assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>,
+                         <&clk IMX8MP_CLK_PCIE_AUX>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+                                <&clk IMX8MP_SYS_PLL2_50M>;
+       status = "okay";
+};
+
+&pcie_phy{
+       status = "okay";
+};
+
 &sai3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai3>;
@@ -852,6 +874,14 @@
                >;
        };
 
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B            0x61 /* open drain, pull up */
+                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06              0x41
+                       MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07              0x41
+               >;
+       };
+
        pinctrl_pmic: pmicirq {
                fsl,pins = <
                        MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x41

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index fe2863e..fc00c9d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/clock/imx8mp-clock.h>
 #include <dt-bindings/reset/imx8mp-reset.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -627,7 +628,8 @@
                        };
 
                        gpr: iomuxc-gpr@30340000 {
-                               compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
+                               compatible = "fsl,imx8mp-iomuxc-gpr",
+                                            "fsl,imx6q-iomuxc-gpr", "syscon";
                                reg = <0x30340000 0x10000>;
                        };
 
@@ -1481,6 +1483,22 @@
                                        status = "disabled";
                                };
                        };
+
+                       pcie_phy: pcie-phy@32f00000 {
+                               compatible = "fsl,imx8mp-pcie-phy";
+                               reg = <0x0 0x32f00000 0x0 0x10000>;
+                               clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
+                               clock-names = "phy";
+                               assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
+                               assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       hsio_mix: hsio-mix@32f10000 {
+                                 compatible = "fsl,imx8mp-hsio-mix";
+                                 reg = <0x0 0x32f10000 0x0 0x8>;
+                       };
                };
 
                aips5: bus@30c00000 {
@@ -1946,6 +1964,40 @@
                        };
                };
 
+               pcie: pcie@33800000 {
+                       compatible = "fsl,imx8mp-pcie", "snps,dw-pcie";
+                       reg = <0x0 0x33800000 0x0 0x400000>,
+                               <0x0 0x1ff00000 0x0 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       ranges =  <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+                                  0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+                       fsl,max-link-speed = <3>;
+                       power-domains = <&pcie_pd>;
+                       resets = <&src IMX8MP_RESET_PCIEPHY>,
+                                <&src IMX8MP_RESET_PCIEPHY_PERST>,
+                                <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
+                                <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+                       reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff";
+                       phys = <&pcie_phy>;
+                       phy-names = "pcie-phy";
+                       fsl,imx8mp-hsio-mix = <&hsio_mix>;
+                       status = "disabled";
+               };
+
                ddr-pmu@3d800000 {
                        compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
                        reg = <0x3d800000 0x400000>;