MLK-9501 dts: imx6sx-sdb: optimize usdhc3 pad settings

Detailed reproduce steps:
1. boot-up to Linux command prompt .
2. Plug SD3.0 UHS-I SD Card into SD3 Connector (make sure SD Card
   running at SD3.0 DDR50/1.8V).
2. write data to SD3 using "dd" command (SD3_CLK running at 1.8V/50MHz).
3. capture the SD3_CLK, SD3_DATA, SD3_CMD waveforms during data write
   using FET probe (>=1GHz)
4. CLK waveforms like triangular wave are observed.

HW team found that the pad setting of the SD3_CLK, SD3_DATA, SD3_CMD
signal pins are not optimized. In existing BSP, when running at
SD3.0/DDR50/1.8V, SPEED/DSE/SRE = 01/011/1 is used.
They propose change it to -  SD3_CLK: SPEED/DSE/SRE = 01/110/1.
SD3_DATA/SD3_CMD: SPEED/DSE/SRE = 01/101/1.

SDHC high speed cards also had such issue(refer to MLK-9500).

We only changed the default state (<50Mhz) pad setting, for ultra high
speed state like 100Mhz and 200Mhz, it does not have such issue since
they already set to the maximum Drive Strength value.

Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 69d4195c741050e0bc78d3005f8ff4f51990d1ae)

Conflicts:
	arch/arm/boot/dts/imx6sx-sdb.dts
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index 0964302..0597637 100644 (file)
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -995,16 +995,16 @@
 
                pinctrl_usdhc3: usdhc3grp {
                        fsl,pins = <
-                               MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
-                               MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
-                               MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
-                               MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
-                               MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
-                               MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
-                               MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
-                               MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
-                               MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
-                               MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
+                               MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17069
+                               MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10071
+                               MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17069
+                               MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17069
+                               MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17069
+                               MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17069
+                               MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17069
+                               MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17069
+                               MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17069
+                               MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17069
                                MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
                                MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
                        >;