MLK-15148 ARM64: dts: freescale: imx8mq: add uart DMA chans and enable BT port
authorFugang Duan <fugang.duan@nxp.com>
Fri, 23 Jun 2017 06:00:41 +0000 (14:00 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 20:28:34 +0000 (15:28 -0500)
Add uart DMA chans for imx8mq platform.
Enable uart3 port for Bluetooth on evk board.
Correct the earlycon name.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi

index 589d01b..6da5a99 100644 (file)
        compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
 
        chosen {
-               bootargs = "console=ttymxc0,115200 earlycon=imxuart,0x30860000,115200";
+               bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
                stdout-path = &uart1;
        };
 
+       modem_reset: modem-reset {
+               compatible = "gpio-reset";
+               reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+               reset-delay-us = <1000>;
+               #reset-cells = <0>;
+       };
+
        wm8524: wm8524 {
                compatible = "wlf,wm8524";
                clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
 
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
-                               MX8MQ_IOMUXC_UART1_RXD_UART1_RX         0x79
-                               MX8MQ_IOMUXC_UART1_TXD_UART1_TX         0x79
+                               MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX             0x79
+                               MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX             0x79
+                       >;
+               };
+
+               pinctrl_uart3: uart3grp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX             0x79
+                               MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX             0x79
+                               MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x79
+                               MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B         0x79
+                               MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5                 0x19
                        >;
                };
 
        };
 };
 
-&uart1 {
+&uart1 { /* console */
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
        assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
        status = "okay";
 };
 
+&uart3 { /* BT */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+       assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+       fsl,uart-has-rtscts;
+       resets = <&modem_reset>;
+       status = "okay";
+};
+
 &usdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1>;
index 5e3bd36..0007609 100644 (file)
@@ -30,6 +30,7 @@
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
+               serial3 = &uart4;
                mmc0 = &usdhc1;
                mmc1 = &usdhc2;
                gpio0 = &gpio1;
                clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
                        <&clk IMX8MQ_CLK_UART3_ROOT>;
                clock-names = "ipg", "per";
+               dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
                        <&clk IMX8MQ_CLK_UART2_ROOT>;
                clock-names = "ipg", "per";
+               dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };
 
                clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
                        <&clk IMX8MQ_CLK_UART4_ROOT>;
                clock-names = "ipg", "per";
+               dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
+               dma-names = "rx", "tx";
                status = "disabled";
        };