MLK-22429 imx8mn: fix audio pll setting

The AUDIO PLL max support 650M, so the original clk settings violate
spec. In order not to impact audio functionality, let's div the
clk by 2.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts
index 774811d..3e44a61 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn-ddr4-evk.dts
@@ -110,7 +110,7 @@
 
 &clk {
        assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>;
-       assigned-clock-rates = <786432000>, <722534400>;
+       assigned-clock-rates = <393216000>, <361267200>;
 };
 
 &easrc {

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 48462de..88d61f7 100644 (file)
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -78,8 +78,8 @@ static const struct imx_pll14xx_rate_table imx8mn_intpll_tbl[] = {
 };
 
 static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
-       PLL_1443X_RATE(786432000U, 262, 2, 2, 9437),
-       PLL_1443X_RATE(722534400U, 361, 3, 2, 17511),
+       PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+       PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
 };
 
 static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {