MLK-12013 arm: imx: set eim_slow clk to 132Mhz only for MXC_CPU_IMX6Q

A patch(set imx6qp eim_slow to 132Mh) was pushed to eliminate
the weim nor read performance drop cause by the IP difference
between imx6q & imx6qp.

However, the patch impacted the performance of imx6dl-ard.
In succession, AXI clk is set to 270M which exceeds the max
value(264M).

This patch sets eim_slow to 132M only for MXC_CPU_IMX6Q. So
the performance difference between imx6q & imx6qp decreases
while no impact for imx6dl-ard.

please see the following summary of weim nor read performance.

clk(performance)	6q-sabreauto	6qp-sabreauto	6dl-ard
imx_3.10        	132M(18.9MB/s)	     ——	     	135M(19.1MB/s)
imx_3.14.y	     	132M(18.9MB/s)	132M(16.8MB/s)	135M(19.1MB/s)

Signed-off-by: Gao Pan <b54642@freescale.com>
(cherry picked from commit f19e9899eacddb5343e7a7d476a500cd4551dffe)

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index da90ee9..218ef9c 100644 (file)
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -883,6 +883,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
                clk_set_rate(clk[IMX6QDL_CLK_IPU2], 200000000);
        } else {
+               /* set eim_slow to 132Mhz for i.MX6Q */
+               if (clk_on_imx6q())
+                       clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 132000000);
                clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
                clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
        }
@@ -896,9 +899,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
        clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
 
-       imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
-       imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]);
-
 
        /*
         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
@@ -953,9 +953,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        if (IS_ENABLED(CONFIG_PCI_IMX6))
                clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
 
-       /* set eim_slow to 135Mhz */
-       imx_clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 135000000);
-
        /*
         * Enable clocks only after both parent and rate are all initialized
         * as needed