MLK-10774-2 HDMI: splash screen function enhancement
authorPeng Fan <Peng.Fan@freescale.com>
Thu, 19 Mar 2015 02:10:07 +0000 (10:10 +0800)
committerYe Li <ye.li@nxp.com>
Thu, 29 Apr 2021 05:03:37 +0000 (22:03 -0700)
-Change HDMI video mode to VGA.
-Add pixel clock fraction part setting in IPU driver,
 fix video mode timing issue.
-Add overflow state clear workaround,
 fix kernel hang in HDMI driver issue.
-Correct IPU clock to 264MHz.

Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5028519b434d5dfbe53c48ac4b115ff8b69bbac7)
(cherry picked from commit 8dcbd43b971616fb67dc3b2af32e2d33f68ed0ce)
(cherry picked from commit 46b20bec72b53f10c1edf0bd8add5b356fbd7c42)
(cherry picked from commit 116691b2fbc7a1f579c1a384739c15aa59e3fa69)
(cherry picked from commit dee071872ea2681a1e824ad78fd7cbe04965febe)

board/freescale/mx6sabresd/mx6sabresd.c

index 53a49c3..a889fa5 100644 (file)
@@ -680,16 +680,16 @@ struct display_info_t const displays[] = {{
        .mode   = {
                .name           = "HDMI",
                .refresh        = 60,
-               .xres           = 1024,
-               .yres           = 768,
-               .pixclock       = 15384,
-               .left_margin    = 160,
-               .right_margin   = 24,
-               .upper_margin   = 29,
-               .lower_margin   = 3,
-               .hsync_len      = 136,
-               .vsync_len      = 6,
-               .sync           = FB_SYNC_EXT,
+               .xres           = 640,
+               .yres           = 480,
+               .pixclock       = 39721,
+               .left_margin    = 48,
+               .right_margin   = 16,
+               .upper_margin   = 33,
+               .lower_margin   = 10,
+               .hsync_len      = 96,
+               .vsync_len      = 2,
+               .sync           = 0,
                .vmode          = FB_VMODE_NONINTERLACED
 } }, {
        .bus    = 0,