/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
- *
- * Peng Fan <peng.fan@nxp.com>
+ * Copyright 2017-2019 NXP
*/
-#ifndef _ASM_ARCH_IMX8M_CLOCK_H
-#define _ASM_ARCH_IMX8M_CLOCK_H
-
#include <linux/bitops.h>
+#ifdef CONFIG_IMX8MQ
+#include <asm/arch/clock_imx8mq.h>
+#else
+#error "Error no clock.h"
+#endif
+
#define MHZ(X) ((X) * 1000000UL)
-enum pll_clocks {
- ANATOP_ARM_PLL,
- ANATOP_GPU_PLL,
- ANATOP_SYSTEM_PLL1,
- ANATOP_SYSTEM_PLL2,
- ANATOP_SYSTEM_PLL3,
- ANATOP_AUDIO_PLL1,
- ANATOP_AUDIO_PLL2,
- ANATOP_VIDEO_PLL1,
- ANATOP_VIDEO_PLL2,
- ANATOP_DRAM_PLL,
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+ MXC_UART_CLK,
+ MXC_QSPI_CLK,
};
enum clk_slice_type {
DRAM_SEL_CLOCK_SLICE,
};
-enum clk_root_index {
- MXC_ARM_CLK = 0,
- ARM_A53_CLK_ROOT = 0,
- ARM_M4_CLK_ROOT = 1,
- VPU_A53_CLK_ROOT = 2,
- GPU_CORE_CLK_ROOT = 3,
- GPU_SHADER_CLK_ROOT = 4,
- MAIN_AXI_CLK_ROOT = 16,
- ENET_AXI_CLK_ROOT = 17,
- NAND_USDHC_BUS_CLK_ROOT = 18,
- VPU_BUS_CLK_ROOT = 19,
- DISPLAY_AXI_CLK_ROOT = 20,
- DISPLAY_APB_CLK_ROOT = 21,
- DISPLAY_RTRM_CLK_ROOT = 22,
- USB_BUS_CLK_ROOT = 23,
- GPU_AXI_CLK_ROOT = 24,
- GPU_AHB_CLK_ROOT = 25,
- NOC_CLK_ROOT = 26,
- NOC_APB_CLK_ROOT = 27,
- AHB_CLK_ROOT = 32,
- IPG_CLK_ROOT = 33,
- MXC_IPG_CLK = 33,
- AUDIO_AHB_CLK_ROOT = 34,
- MIPI_DSI_ESC_RX_CLK_ROOT = 36,
- DRAM_SEL_CFG = 48,
- CORE_SEL_CFG = 49,
- DRAM_ALT_CLK_ROOT = 64,
- DRAM_APB_CLK_ROOT = 65,
- VPU_G1_CLK_ROOT = 66,
- VPU_G2_CLK_ROOT = 67,
- DISPLAY_DTRC_CLK_ROOT = 68,
- DISPLAY_DC8000_CLK_ROOT = 69,
- PCIE1_CTRL_CLK_ROOT = 70,
- PCIE1_PHY_CLK_ROOT = 71,
- PCIE1_AUX_CLK_ROOT = 72,
- DC_PIXEL_CLK_ROOT = 73,
- LCDIF_PIXEL_CLK_ROOT = 74,
- SAI1_CLK_ROOT = 75,
- SAI2_CLK_ROOT = 76,
- SAI3_CLK_ROOT = 77,
- SAI4_CLK_ROOT = 78,
- SAI5_CLK_ROOT = 79,
- SAI6_CLK_ROOT = 80,
- SPDIF1_CLK_ROOT = 81,
- SPDIF2_CLK_ROOT = 82,
- ENET_REF_CLK_ROOT = 83,
- ENET_TIMER_CLK_ROOT = 84,
- ENET_PHY_REF_CLK_ROOT = 85,
- NAND_CLK_ROOT = 86,
- QSPI_CLK_ROOT = 87,
- MXC_ESDHC_CLK = 88,
- USDHC1_CLK_ROOT = 88,
- MXC_ESDHC2_CLK = 89,
- USDHC2_CLK_ROOT = 89,
- I2C1_CLK_ROOT = 90,
- MXC_I2C_CLK = 90,
- I2C2_CLK_ROOT = 91,
- I2C3_CLK_ROOT = 92,
- I2C4_CLK_ROOT = 93,
- UART1_CLK_ROOT = 94,
- UART2_CLK_ROOT = 95,
- UART3_CLK_ROOT = 96,
- UART4_CLK_ROOT = 97,
- USB_CORE_REF_CLK_ROOT = 98,
- USB_PHY_REF_CLK_ROOT = 99,
- GIC_CLK_ROOT = 100,
- ECSPI1_CLK_ROOT = 101,
- ECSPI2_CLK_ROOT = 102,
- PWM1_CLK_ROOT = 103,
- PWM2_CLK_ROOT = 104,
- PWM3_CLK_ROOT = 105,
- PWM4_CLK_ROOT = 106,
- GPT1_CLK_ROOT = 107,
- GPT2_CLK_ROOT = 108,
- GPT3_CLK_ROOT = 109,
- GPT4_CLK_ROOT = 110,
- GPT5_CLK_ROOT = 111,
- GPT6_CLK_ROOT = 112,
- TRACE_CLK_ROOT = 113,
- WDOG_CLK_ROOT = 114,
- WRCLK_CLK_ROOT = 115,
- IPP_DO_CLKO1 = 116,
- IPP_DO_CLKO2 = 117,
- MIPI_DSI_CORE_CLK_ROOT = 118,
- MIPI_DSI_PHY_REF_CLK_ROOT = 119,
- MIPI_DSI_DBI_CLK_ROOT = 120,
- OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
- MIPI_CSI1_CORE_CLK_ROOT = 122,
- MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
- MIPI_CSI1_ESC_CLK_ROOT = 124,
- MIPI_CSI2_CORE_CLK_ROOT = 125,
- MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
- MIPI_CSI2_ESC_CLK_ROOT = 127,
- PCIE2_CTRL_CLK_ROOT = 128,
- PCIE2_PHY_CLK_ROOT = 129,
- PCIE2_AUX_CLK_ROOT = 130,
- ECSPI3_CLK_ROOT = 131,
- OLD_MIPI_DSI_ESC_RX_ROOT = 132,
- DISPLAY_HDMI_CLK_ROOT = 133,
- CLK_ROOT_MAX,
-};
-
-enum clk_root_src {
- OSC_25M_CLK,
- ARM_PLL_CLK,
- DRAM_PLL1_CLK,
- VIDEO_PLL2_CLK,
- VPU_PLL_CLK,
- GPU_PLL_CLK,
- SYSTEM_PLL1_800M_CLK,
- SYSTEM_PLL1_400M_CLK,
- SYSTEM_PLL1_266M_CLK,
- SYSTEM_PLL1_200M_CLK,
- SYSTEM_PLL1_160M_CLK,
- SYSTEM_PLL1_133M_CLK,
- SYSTEM_PLL1_100M_CLK,
- SYSTEM_PLL1_80M_CLK,
- SYSTEM_PLL1_40M_CLK,
- SYSTEM_PLL2_1000M_CLK,
- SYSTEM_PLL2_500M_CLK,
- SYSTEM_PLL2_333M_CLK,
- SYSTEM_PLL2_250M_CLK,
- SYSTEM_PLL2_200M_CLK,
- SYSTEM_PLL2_166M_CLK,
- SYSTEM_PLL2_125M_CLK,
- SYSTEM_PLL2_100M_CLK,
- SYSTEM_PLL2_50M_CLK,
- SYSTEM_PLL3_CLK,
- AUDIO_PLL1_CLK,
- AUDIO_PLL2_CLK,
- VIDEO_PLL_CLK,
- OSC_32K_CLK,
- EXT_CLK_1,
- EXT_CLK_2,
- EXT_CLK_3,
- EXT_CLK_4,
- OSC_27M_CLK,
-};
-
-/* CCGR index */
-enum clk_ccgr_index {
- CCGR_DVFS = 0,
- CCGR_ANAMIX = 1,
- CCGR_CPU = 2,
- CCGR_CSU = 4,
- CCGR_DRAM1 = 5,
- CCGR_DRAM2_OBSOLETE = 6,
- CCGR_ECSPI1 = 7,
- CCGR_ECSPI2 = 8,
- CCGR_ECSPI3 = 9,
- CCGR_ENET1 = 10,
- CCGR_GPIO1 = 11,
- CCGR_GPIO2 = 12,
- CCGR_GPIO3 = 13,
- CCGR_GPIO4 = 14,
- CCGR_GPIO5 = 15,
- CCGR_GPT1 = 16,
- CCGR_GPT2 = 17,
- CCGR_GPT3 = 18,
- CCGR_GPT4 = 19,
- CCGR_GPT5 = 20,
- CCGR_GPT6 = 21,
- CCGR_HS = 22,
- CCGR_I2C1 = 23,
- CCGR_I2C2 = 24,
- CCGR_I2C3 = 25,
- CCGR_I2C4 = 26,
- CCGR_IOMUX = 27,
- CCGR_IOMUX1 = 28,
- CCGR_IOMUX2 = 29,
- CCGR_IOMUX3 = 30,
- CCGR_IOMUX4 = 31,
- CCGR_M4 = 32,
- CCGR_MU = 33,
- CCGR_OCOTP = 34,
- CCGR_OCRAM = 35,
- CCGR_OCRAM_S = 36,
- CCGR_PCIE = 37,
- CCGR_PERFMON1 = 38,
- CCGR_PERFMON2 = 39,
- CCGR_PWM1 = 40,
- CCGR_PWM2 = 41,
- CCGR_PWM3 = 42,
- CCGR_PWM4 = 43,
- CCGR_QOS = 44,
- CCGR_DISMIX = 45,
- CCGR_MEGAMIX = 46,
- CCGR_QSPI = 47,
- CCGR_RAWNAND = 48,
- CCGR_RDC = 49,
- CCGR_ROM = 50,
- CCGR_SAI1 = 51,
- CCGR_SAI2 = 52,
- CCGR_SAI3 = 53,
- CCGR_SAI4 = 54,
- CCGR_SAI5 = 55,
- CCGR_SAI6 = 56,
- CCGR_SCTR = 57,
- CCGR_SDMA1 = 58,
- CCGR_SDMA2 = 59,
- CCGR_SEC_DEBUG = 60,
- CCGR_SEMA1 = 61,
- CCGR_SEMA2 = 62,
- CCGR_SIM_DISPLAY = 63,
- CCGR_SIM_ENET = 64,
- CCGR_SIM_M = 65,
- CCGR_SIM_MAIN = 66,
- CCGR_SIM_S = 67,
- CCGR_SIM_WAKEUP = 68,
- CCGR_SIM_USB = 69,
- CCGR_SIM_VPU = 70,
- CCGR_SNVS = 71,
- CCGR_TRACE = 72,
- CCGR_UART1 = 73,
- CCGR_UART2 = 74,
- CCGR_UART3 = 75,
- CCGR_UART4 = 76,
- CCGR_USB_CTRL1 = 77,
- CCGR_USB_CTRL2 = 78,
- CCGR_USB_PHY1 = 79,
- CCGR_USB_PHY2 = 80,
- CCGR_USDHC1 = 81,
- CCGR_USDHC2 = 82,
- CCGR_WDOG1 = 83,
- CCGR_WDOG2 = 84,
- CCGR_WDOG3 = 85,
- CCGR_VA53 = 86,
- CCGR_GPU = 87,
- CCGR_HEVC = 88,
- CCGR_AVC = 89,
- CCGR_VP9 = 90,
- CCGR_HEVC_INTER = 91,
- CCGR_GIC = 92,
- CCGR_DISPLAY = 93,
- CCGR_HDMI = 94,
- CCGR_HDMI_PHY = 95,
- CCGR_XTAL = 96,
- CCGR_PLL = 97,
- CCGR_TSENSOR = 98,
- CCGR_VPU_DEC = 99,
- CCGR_PCIE2 = 100,
- CCGR_MIPI_CSI1 = 101,
- CCGR_MIPI_CSI2 = 102,
- CCGR_MAX,
-};
-
-/* src index */
-enum clk_src_index {
- CLK_SRC_CKIL_SYNC_REQ = 0,
- CLK_SRC_ARM_PLL_EN = 1,
- CLK_SRC_GPU_PLL_EN = 2,
- CLK_SRC_VPU_PLL_EN = 3,
- CLK_SRC_DRAM_PLL_EN = 4,
- CLK_SRC_SYSTEM_PLL1_EN = 5,
- CLK_SRC_SYSTEM_PLL2_EN = 6,
- CLK_SRC_SYSTEM_PLL3_EN = 7,
- CLK_SRC_AUDIO_PLL1_EN = 8,
- CLK_SRC_AUDIO_PLL2_EN = 9,
- CLK_SRC_VIDEO_PLL1_EN = 10,
- CLK_SRC_VIDEO_PLL2_EN = 11,
- CLK_SRC_ARM_PLL = 12,
- CLK_SRC_GPU_PLL = 13,
- CLK_SRC_VPU_PLL = 14,
- CLK_SRC_DRAM_PLL = 15,
- CLK_SRC_SYSTEM_PLL1_800M = 16,
- CLK_SRC_SYSTEM_PLL1_400M = 17,
- CLK_SRC_SYSTEM_PLL1_266M = 18,
- CLK_SRC_SYSTEM_PLL1_200M = 19,
- CLK_SRC_SYSTEM_PLL1_160M = 20,
- CLK_SRC_SYSTEM_PLL1_133M = 21,
- CLK_SRC_SYSTEM_PLL1_100M = 22,
- CLK_SRC_SYSTEM_PLL1_80M = 23,
- CLK_SRC_SYSTEM_PLL1_40M = 24,
- CLK_SRC_SYSTEM_PLL2_1000M = 25,
- CLK_SRC_SYSTEM_PLL2_500M = 26,
- CLK_SRC_SYSTEM_PLL2_333M = 27,
- CLK_SRC_SYSTEM_PLL2_250M = 28,
- CLK_SRC_SYSTEM_PLL2_200M = 29,
- CLK_SRC_SYSTEM_PLL2_166M = 30,
- CLK_SRC_SYSTEM_PLL2_125M = 31,
- CLK_SRC_SYSTEM_PLL2_100M = 32,
- CLK_SRC_SYSTEM_PLL2_50M = 33,
- CLK_SRC_SYSTEM_PLL3 = 34,
- CLK_SRC_AUDIO_PLL1 = 35,
- CLK_SRC_AUDIO_PLL2 = 36,
- CLK_SRC_VIDEO_PLL1 = 37,
- CLK_SRC_VIDEO_PLL2 = 38,
- CLK_SRC_OSC_25M = 39,
- CLK_SRC_OSC_27M = 40,
-};
-
enum root_pre_div {
CLK_ROOT_PRE_DIV1 = 0,
CLK_ROOT_PRE_DIV2,
struct ccm_root ip_root[78];
};
+enum enet_freq {
+ ENET_25MHZ = 0,
+ ENET_50MHZ,
+ ENET_125MHZ,
+};
+
+#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
+ { \
+ .clk = (_rate), \
+ .alt_root_sel = (_m), \
+ .alt_pre_div = (_p), \
+ .apb_root_sel = (_s), \
+ .apb_pre_div = (_k), \
+ }
+
+struct dram_bypass_clk_setting {
+ ulong clk;
+ int alt_root_sel;
+ enum root_pre_div alt_pre_div;
+ int apb_root_sel;
+ enum root_pre_div apb_pre_div;
+};
+
#define CCGR_CLK_ON_MASK 0x03
#define CLK_SRC_ON_MASK 0x03
#define CLK_ROOT_POST_DIV_SHIFT 0
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
-/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
-#define FRAC_PLL_LOCK_MASK BIT(31)
-#define FRAC_PLL_CLKE_MASK BIT(21)
-#define FRAC_PLL_PD_MASK BIT(19)
-#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
-#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
-#define FRAC_PLL_BYPASS_MASK BIT(14)
-#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
-#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
-#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
-#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
-#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
-#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
-#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
-#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
-
-#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
-#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
-#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
-
-#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
-#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
-#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
-#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
-
-/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
-#define SSCG_PLL_LOCK_MASK BIT(31)
-#define SSCG_PLL_CLKE_MASK BIT(25)
-#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
-#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
-#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
-#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
-#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
-#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
-#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
-#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
-#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
-#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
-#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
-#define SSCG_PLL_PD_MASK BIT(7)
-#define SSCG_PLL_BYPASS1_MASK BIT(5)
-#define SSCG_PLL_BYPASS2_MASK BIT(4)
-#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
-#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
-#define SSCG_PLL_REFCLK_SEL_MASK 0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
-
-#define SSCG_PLL_SSDS_MASK BIT(8)
-#define SSCG_PLL_SSMD_MASK (0x7 << 5)
-#define SSCG_PLL_SSMF_MASK (0xf << 1)
-#define SSCG_PLL_SSE_MASK 0x1
-
-#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
-#define SSCG_PLL_REF_DIVR1_SHIFT 25
-#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
-#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
-#define SSCG_PLL_REF_DIVR2_SHIFT 19
-#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
-#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
-#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
- SSCG_PLL_FEEDBACK_DIV_F1_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
-#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
-#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
- SSCG_PLL_FEEDBACK_DIV_F2_MASK)
-#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
-#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
-#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
- SSCG_PLL_OUTPUT_DIV_VAL_MASK)
-#define SSCG_PLL_FILTER_RANGE_MASK 0x1
-
-#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
-#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
-#define HW_DIGPROG_MINOR_MASK 0xff
-
-#define HW_OSC_27M_CLKE_MASK BIT(4)
-#define HW_OSC_25M_CLKE_MASK BIT(2)
-#define HW_OSC_32K_SEL_MASK 0x1
-#define HW_OSC_32K_SEL_RTC 0x1
-#define HW_OSC_32K_SEL_25M_DIV800 0x0
-
-#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
-#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
-#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
-#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
-#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
-#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
-#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
-#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
-#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
-#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
-#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
-#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
-
-#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
-#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
-#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
-#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
-#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
-#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
-#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
-#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
-#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
-#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
-
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
-enum enet_freq {
- ENET_25MHZ = 0,
- ENET_50MHZ,
- ENET_125MHZ,
-};
-
-enum frac_pll_out_val {
- FRAC_PLL_OUT_1000M,
- FRAC_PLL_OUT_1600M,
-};
-
-#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
- { \
- .clk = (_rate), \
- .alt_root_sel = (_m), \
- .alt_pre_div = (_p), \
- .apb_root_sel = (_s), \
- .apb_pre_div = (_k), \
- }
-
-struct dram_bypass_clk_setting {
- ulong clk;
- int alt_root_sel;
- enum root_pre_div alt_pre_div;
- int apb_root_sel;
- enum root_pre_div apb_pre_div;
-};
-
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
void init_uart_clk(u32 index);
void init_usb_clk(void);
void init_wdog_clk(void);
-unsigned int mxc_get_clock(enum clk_root_index clk);
+void init_clk_ecspi(u32 index);
+unsigned int mxc_get_clock(enum mxc_clock clk);
int clock_enable(enum clk_ccgr_index index, bool enable);
int clock_root_enabled(enum clk_root_index clock_id);
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
int set_clk_enet(enum enet_freq type);
void hab_caam_clock_enable(unsigned char enable);
-#endif
+void enable_usboh3_clk(unsigned char enable);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+enum pll_clocks {
+ ANATOP_ARM_PLL,
+ ANATOP_GPU_PLL,
+ ANATOP_SYSTEM_PLL1,
+ ANATOP_SYSTEM_PLL2,
+ ANATOP_SYSTEM_PLL3,
+ ANATOP_AUDIO_PLL1,
+ ANATOP_AUDIO_PLL2,
+ ANATOP_VIDEO_PLL1,
+ ANATOP_VIDEO_PLL2,
+ ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+ ARM_A53_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ VPU_A53_CLK_ROOT = 2,
+ GPU_CORE_CLK_ROOT = 3,
+ GPU_SHADER_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ VPU_BUS_CLK_ROOT = 19,
+ DISPLAY_AXI_CLK_ROOT = 20,
+ DISPLAY_APB_CLK_ROOT = 21,
+ DISPLAY_RTRM_CLK_ROOT = 22,
+ USB_BUS_CLK_ROOT = 23,
+ GPU_AXI_CLK_ROOT = 24,
+ GPU_AHB_CLK_ROOT = 25,
+ NOC_CLK_ROOT = 26,
+ NOC_APB_CLK_ROOT = 27,
+ AHB_CLK_ROOT = 32,
+ IPG_CLK_ROOT = 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ MIPI_DSI_ESC_RX_CLK_ROOT = 36,
+ DRAM_SEL_CFG = 48,
+ CORE_SEL_CFG = 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ VPU_G1_CLK_ROOT = 66,
+ VPU_G2_CLK_ROOT = 67,
+ DISPLAY_DTRC_CLK_ROOT = 68,
+ DISPLAY_DC8000_CLK_ROOT = 69,
+ PCIE1_CTRL_CLK_ROOT = 70,
+ PCIE1_PHY_CLK_ROOT = 71,
+ PCIE1_AUX_CLK_ROOT = 72,
+ DC_PIXEL_CLK_ROOT = 73,
+ LCDIF_PIXEL_CLK_ROOT = 74,
+ SAI1_CLK_ROOT = 75,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI4_CLK_ROOT = 78,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ SPDIF2_CLK_ROOT = 82,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT = 87,
+ USDHC1_CLK_ROOT = 88,
+ USDHC2_CLK_ROOT = 89,
+ I2C1_CLK_ROOT = 90,
+ I2C2_CLK_ROOT = 91,
+ I2C3_CLK_ROOT = 92,
+ I2C4_CLK_ROOT = 93,
+ UART1_CLK_ROOT = 94,
+ UART2_CLK_ROOT = 95,
+ UART3_CLK_ROOT = 96,
+ UART4_CLK_ROOT = 97,
+ USB_CORE_REF_CLK_ROOT = 98,
+ USB_PHY_REF_CLK_ROOT = 99,
+ GIC_CLK_ROOT = 100,
+ ECSPI1_CLK_ROOT = 101,
+ ECSPI2_CLK_ROOT = 102,
+ PWM1_CLK_ROOT = 103,
+ PWM2_CLK_ROOT = 104,
+ PWM3_CLK_ROOT = 105,
+ PWM4_CLK_ROOT = 106,
+ GPT1_CLK_ROOT = 107,
+ GPT2_CLK_ROOT = 108,
+ GPT3_CLK_ROOT = 109,
+ GPT4_CLK_ROOT = 110,
+ GPT5_CLK_ROOT = 111,
+ GPT6_CLK_ROOT = 112,
+ TRACE_CLK_ROOT = 113,
+ WDOG_CLK_ROOT = 114,
+ WRCLK_CLK_ROOT = 115,
+ IPP_DO_CLKO1 = 116,
+ IPP_DO_CLKO2 = 117,
+ MIPI_DSI_CORE_CLK_ROOT = 118,
+ MIPI_DSI_PHY_REF_CLK_ROOT = 119,
+ MIPI_DSI_DBI_CLK_ROOT = 120,
+ OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
+ MIPI_CSI1_CORE_CLK_ROOT = 122,
+ MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
+ MIPI_CSI1_ESC_CLK_ROOT = 124,
+ MIPI_CSI2_CORE_CLK_ROOT = 125,
+ MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
+ MIPI_CSI2_ESC_CLK_ROOT = 127,
+ PCIE2_CTRL_CLK_ROOT = 128,
+ PCIE2_PHY_CLK_ROOT = 129,
+ PCIE2_AUX_CLK_ROOT = 130,
+ ECSPI3_CLK_ROOT = 131,
+ OLD_MIPI_DSI_ESC_RX_ROOT = 132,
+ DISPLAY_HDMI_CLK_ROOT = 133,
+ CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+ OSC_25M_CLK,
+ ARM_PLL_CLK,
+ DRAM_PLL1_CLK,
+ VIDEO_PLL2_CLK,
+ VPU_PLL_CLK,
+ GPU_PLL_CLK,
+ SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_266M_CLK,
+ SYSTEM_PLL1_200M_CLK,
+ SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK,
+ AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK,
+ OSC_32K_CLK,
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+ OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+ CCGR_DVFS = 0,
+ CCGR_ANAMIX = 1,
+ CCGR_CPU = 2,
+ CCGR_CSU = 4,
+ CCGR_DRAM1 = 5,
+ CCGR_DRAM2_OBSOLETE = 6,
+ CCGR_ECSPI1 = 7,
+ CCGR_ECSPI2 = 8,
+ CCGR_ECSPI3 = 9,
+ CCGR_ENET1 = 10,
+ CCGR_GPIO1 = 11,
+ CCGR_GPIO2 = 12,
+ CCGR_GPIO3 = 13,
+ CCGR_GPIO4 = 14,
+ CCGR_GPIO5 = 15,
+ CCGR_GPT1 = 16,
+ CCGR_GPT2 = 17,
+ CCGR_GPT3 = 18,
+ CCGR_GPT4 = 19,
+ CCGR_GPT5 = 20,
+ CCGR_GPT6 = 21,
+ CCGR_HS = 22,
+ CCGR_I2C1 = 23,
+ CCGR_I2C2 = 24,
+ CCGR_I2C3 = 25,
+ CCGR_I2C4 = 26,
+ CCGR_IOMUX = 27,
+ CCGR_IOMUX1 = 28,
+ CCGR_IOMUX2 = 29,
+ CCGR_IOMUX3 = 30,
+ CCGR_IOMUX4 = 31,
+ CCGR_M4 = 32,
+ CCGR_MU = 33,
+ CCGR_OCOTP = 34,
+ CCGR_OCRAM = 35,
+ CCGR_OCRAM_S = 36,
+ CCGR_PCIE = 37,
+ CCGR_PERFMON1 = 38,
+ CCGR_PERFMON2 = 39,
+ CCGR_PWM1 = 40,
+ CCGR_PWM2 = 41,
+ CCGR_PWM3 = 42,
+ CCGR_PWM4 = 43,
+ CCGR_QOS = 44,
+ CCGR_DISMIX = 45,
+ CCGR_MEGAMIX = 46,
+ CCGR_QSPI = 47,
+ CCGR_RAWNAND = 48,
+ CCGR_RDC = 49,
+ CCGR_ROM = 50,
+ CCGR_SAI1 = 51,
+ CCGR_SAI2 = 52,
+ CCGR_SAI3 = 53,
+ CCGR_SAI4 = 54,
+ CCGR_SAI5 = 55,
+ CCGR_SAI6 = 56,
+ CCGR_SCTR = 57,
+ CCGR_SDMA1 = 58,
+ CCGR_SDMA2 = 59,
+ CCGR_SEC_DEBUG = 60,
+ CCGR_SEMA1 = 61,
+ CCGR_SEMA2 = 62,
+ CCGR_SIM_DISPLAY = 63,
+ CCGR_SIM_ENET = 64,
+ CCGR_SIM_M = 65,
+ CCGR_SIM_MAIN = 66,
+ CCGR_SIM_S = 67,
+ CCGR_SIM_WAKEUP = 68,
+ CCGR_SIM_USB = 69,
+ CCGR_SIM_VPU = 70,
+ CCGR_SNVS = 71,
+ CCGR_TRACE = 72,
+ CCGR_UART1 = 73,
+ CCGR_UART2 = 74,
+ CCGR_UART3 = 75,
+ CCGR_UART4 = 76,
+ CCGR_USB_CTRL1 = 77,
+ CCGR_USB_CTRL2 = 78,
+ CCGR_USB_PHY1 = 79,
+ CCGR_USB_PHY2 = 80,
+ CCGR_USDHC1 = 81,
+ CCGR_USDHC2 = 82,
+ CCGR_WDOG1 = 83,
+ CCGR_WDOG2 = 84,
+ CCGR_WDOG3 = 85,
+ CCGR_VA53 = 86,
+ CCGR_GPU = 87,
+ CCGR_HEVC = 88,
+ CCGR_AVC = 89,
+ CCGR_VP9 = 90,
+ CCGR_HEVC_INTER = 91,
+ CCGR_GIC = 92,
+ CCGR_DISPLAY = 93,
+ CCGR_HDMI = 94,
+ CCGR_HDMI_PHY = 95,
+ CCGR_XTAL = 96,
+ CCGR_PLL = 97,
+ CCGR_TSENSOR = 98,
+ CCGR_VPU_DEC = 99,
+ CCGR_PCIE2 = 100,
+ CCGR_MIPI_CSI1 = 101,
+ CCGR_MIPI_CSI2 = 102,
+ CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+ CLK_SRC_CKIL_SYNC_REQ = 0,
+ CLK_SRC_ARM_PLL_EN = 1,
+ CLK_SRC_GPU_PLL_EN = 2,
+ CLK_SRC_VPU_PLL_EN = 3,
+ CLK_SRC_DRAM_PLL_EN = 4,
+ CLK_SRC_SYSTEM_PLL1_EN = 5,
+ CLK_SRC_SYSTEM_PLL2_EN = 6,
+ CLK_SRC_SYSTEM_PLL3_EN = 7,
+ CLK_SRC_AUDIO_PLL1_EN = 8,
+ CLK_SRC_AUDIO_PLL2_EN = 9,
+ CLK_SRC_VIDEO_PLL1_EN = 10,
+ CLK_SRC_VIDEO_PLL2_EN = 11,
+ CLK_SRC_ARM_PLL = 12,
+ CLK_SRC_GPU_PLL = 13,
+ CLK_SRC_VPU_PLL = 14,
+ CLK_SRC_DRAM_PLL = 15,
+ CLK_SRC_SYSTEM_PLL1_800M = 16,
+ CLK_SRC_SYSTEM_PLL1_400M = 17,
+ CLK_SRC_SYSTEM_PLL1_266M = 18,
+ CLK_SRC_SYSTEM_PLL1_200M = 19,
+ CLK_SRC_SYSTEM_PLL1_160M = 20,
+ CLK_SRC_SYSTEM_PLL1_133M = 21,
+ CLK_SRC_SYSTEM_PLL1_100M = 22,
+ CLK_SRC_SYSTEM_PLL1_80M = 23,
+ CLK_SRC_SYSTEM_PLL1_40M = 24,
+ CLK_SRC_SYSTEM_PLL2_1000M = 25,
+ CLK_SRC_SYSTEM_PLL2_500M = 26,
+ CLK_SRC_SYSTEM_PLL2_333M = 27,
+ CLK_SRC_SYSTEM_PLL2_250M = 28,
+ CLK_SRC_SYSTEM_PLL2_200M = 29,
+ CLK_SRC_SYSTEM_PLL2_166M = 30,
+ CLK_SRC_SYSTEM_PLL2_125M = 31,
+ CLK_SRC_SYSTEM_PLL2_100M = 32,
+ CLK_SRC_SYSTEM_PLL2_50M = 33,
+ CLK_SRC_SYSTEM_PLL3 = 34,
+ CLK_SRC_AUDIO_PLL1 = 35,
+ CLK_SRC_AUDIO_PLL2 = 36,
+ CLK_SRC_VIDEO_PLL1 = 37,
+ CLK_SRC_VIDEO_PLL2 = 38,
+ CLK_SRC_OSC_25M = 39,
+ CLK_SRC_OSC_27M = 40,
+};
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK BIT(31)
+#define FRAC_PLL_CLKE_MASK BIT(21)
+#define FRAC_PLL_PD_MASK BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
+#define FRAC_PLL_BYPASS_MASK BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
+#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK BIT(31)
+#define SSCG_PLL_CLKE_MASK BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
+#define SSCG_PLL_PD_MASK BIT(7)
+#define SSCG_PLL_BYPASS1_MASK BIT(5)
+#define SSCG_PLL_BYPASS2_MASK BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK 0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define SSCG_PLL_SSDS_MASK BIT(8)
+#define SSCG_PLL_SSMD_MASK (0x7 << 5)
+#define SSCG_PLL_SSMF_MASK (0xf << 1)
+#define SSCG_PLL_SSE_MASK 0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT 25
+#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT 19
+#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
+ SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK 0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
+#define HW_DIGPROG_MINOR_MASK 0xff
+
+#define HW_OSC_27M_CLKE_MASK BIT(4)
+#define HW_OSC_25M_CLKE_MASK BIT(2)
+#define HW_OSC_32K_SEL_MASK 0x1
+#define HW_OSC_32K_SEL_RTC 0x1
+#define HW_OSC_32K_SEL_25M_DIV800 0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
+#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
+#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
+#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
+
+enum frac_pll_out_val {
+ FRAC_PLL_OUT_1000M,
+ FRAC_PLL_OUT_1600M,
+};
+
+#endif
# Copyright 2017 NXP
obj-y += lowlevel_init.o
-obj-y += clock.o clock_slice.o soc.o
+obj-y += clock_slice.o soc.o
+obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
obj-$(CONFIG_VIDEO_IMXDCSS) += video_common.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2017 NXP
- *
- * Peng Fan <peng.fan@nxp.com>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <errno.h>
-#include <linux/iopoll.h>
-
-static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
-
-static u32 decode_frac_pll(enum clk_root_src frac_pll)
-{
- u32 pll_cfg0, pll_cfg1, pllout;
- u32 pll_refclk_sel, pll_refclk;
- u32 divr_val, divq_val, divf_val, divff, divfi;
- u32 pllout_div_shift, pllout_div_mask, pllout_div;
-
- switch (frac_pll) {
- case ARM_PLL_CLK:
- pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
- pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
- pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
- pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
- break;
- default:
- printf("Frac PLL %d not supporte\n", frac_pll);
- return 0;
- }
-
- pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
- pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
-
- /* Power down */
- if (pll_cfg0 & FRAC_PLL_PD_MASK)
- return 0;
-
- /* output not enabled */
- if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
- return 0;
-
- pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
-
- if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
- pll_refclk = 25000000u;
- else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
- pll_refclk = 27000000u;
- else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
- pll_refclk = 27000000u;
- else
- pll_refclk = 0;
-
- if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
- return pll_refclk;
-
- divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
- FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
- divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
-
- divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
- FRAC_PLL_FRAC_DIV_CTL_SHIFT;
- divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
-
- divf_val = 1 + divfi + divff / (1 << 24);
-
- pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
- ((divq_val + 1) * 2);
-
- return pllout / (pllout_div + 1);
-}
-
-static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
-{
- u32 pll_cfg0, pll_cfg1, pll_cfg2;
- u32 pll_refclk_sel, pll_refclk;
- u32 divr1, divr2, divf1, divf2, divq, div;
- u32 sse;
- u32 pll_clke;
- u32 pllout_div_shift, pllout_div_mask, pllout_div;
- u32 pllout;
-
- switch (sscg_pll) {
- case SYSTEM_PLL1_800M_CLK:
- case SYSTEM_PLL1_400M_CLK:
- case SYSTEM_PLL1_266M_CLK:
- case SYSTEM_PLL1_200M_CLK:
- case SYSTEM_PLL1_160M_CLK:
- case SYSTEM_PLL1_133M_CLK:
- case SYSTEM_PLL1_100M_CLK:
- case SYSTEM_PLL1_80M_CLK:
- case SYSTEM_PLL1_40M_CLK:
- pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
- pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
- pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
- pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
- pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
- break;
- case SYSTEM_PLL2_1000M_CLK:
- case SYSTEM_PLL2_500M_CLK:
- case SYSTEM_PLL2_333M_CLK:
- case SYSTEM_PLL2_250M_CLK:
- case SYSTEM_PLL2_200M_CLK:
- case SYSTEM_PLL2_166M_CLK:
- case SYSTEM_PLL2_125M_CLK:
- case SYSTEM_PLL2_100M_CLK:
- case SYSTEM_PLL2_50M_CLK:
- pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
- pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
- pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
- pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
- pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
- break;
- case SYSTEM_PLL3_CLK:
- pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
- pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
- pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
- pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
- pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
- break;
- case DRAM_PLL1_CLK:
- pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
- pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
- pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
- pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
- pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
- break;
- default:
- printf("sscg pll %d not supporte\n", sscg_pll);
- return 0;
- }
-
- switch (sscg_pll) {
- case DRAM_PLL1_CLK:
- pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
- div = 1;
- break;
- case SYSTEM_PLL3_CLK:
- pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
- div = 1;
- break;
- case SYSTEM_PLL2_1000M_CLK:
- case SYSTEM_PLL1_800M_CLK:
- pll_clke = SSCG_PLL_CLKE_MASK;
- div = 1;
- break;
- case SYSTEM_PLL2_500M_CLK:
- case SYSTEM_PLL1_400M_CLK:
- pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
- div = 2;
- break;
- case SYSTEM_PLL2_333M_CLK:
- case SYSTEM_PLL1_266M_CLK:
- pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
- div = 3;
- break;
- case SYSTEM_PLL2_250M_CLK:
- case SYSTEM_PLL1_200M_CLK:
- pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
- div = 4;
- break;
- case SYSTEM_PLL2_200M_CLK:
- case SYSTEM_PLL1_160M_CLK:
- pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
- div = 5;
- break;
- case SYSTEM_PLL2_166M_CLK:
- case SYSTEM_PLL1_133M_CLK:
- pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
- div = 6;
- break;
- case SYSTEM_PLL2_125M_CLK:
- case SYSTEM_PLL1_100M_CLK:
- pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
- div = 8;
- break;
- case SYSTEM_PLL2_100M_CLK:
- case SYSTEM_PLL1_80M_CLK:
- pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
- div = 10;
- break;
- case SYSTEM_PLL2_50M_CLK:
- case SYSTEM_PLL1_40M_CLK:
- pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
- div = 20;
- break;
- default:
- printf("sscg pll %d not supporte\n", sscg_pll);
- return 0;
- }
-
- /* Power down */
- if (pll_cfg0 & SSCG_PLL_PD_MASK)
- return 0;
-
- /* output not enabled */
- if ((pll_cfg0 & pll_clke) == 0)
- return 0;
-
- pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
- pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
-
- pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
-
- if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
- pll_refclk = 25000000u;
- else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
- pll_refclk = 27000000u;
- else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
- pll_refclk = 27000000u;
- else
- pll_refclk = 0;
-
- /* We assume bypass1/2 are the same value */
- if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
- (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
- return pll_refclk;
-
- divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
- SSCG_PLL_REF_DIVR1_SHIFT;
- divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
- SSCG_PLL_REF_DIVR2_SHIFT;
- divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
- SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
- divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
- SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
- divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
- SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
- sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
-
- if (sse)
- sse = 8;
- else
- sse = 2;
-
- pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
- (divr2 + 1) * (divf2 + 1) / (divq + 1);
-
- return pllout / (pllout_div + 1) / div;
-}
-
-static u32 get_root_src_clk(enum clk_root_src root_src)
-{
- switch (root_src) {
- case OSC_25M_CLK:
- return 25000000;
- case OSC_27M_CLK:
- return 27000000;
- case OSC_32K_CLK:
- return 32768;
- case ARM_PLL_CLK:
- return decode_frac_pll(root_src);
- case SYSTEM_PLL1_800M_CLK:
- case SYSTEM_PLL1_400M_CLK:
- case SYSTEM_PLL1_266M_CLK:
- case SYSTEM_PLL1_200M_CLK:
- case SYSTEM_PLL1_160M_CLK:
- case SYSTEM_PLL1_133M_CLK:
- case SYSTEM_PLL1_100M_CLK:
- case SYSTEM_PLL1_80M_CLK:
- case SYSTEM_PLL1_40M_CLK:
- case SYSTEM_PLL2_1000M_CLK:
- case SYSTEM_PLL2_500M_CLK:
- case SYSTEM_PLL2_333M_CLK:
- case SYSTEM_PLL2_250M_CLK:
- case SYSTEM_PLL2_200M_CLK:
- case SYSTEM_PLL2_166M_CLK:
- case SYSTEM_PLL2_125M_CLK:
- case SYSTEM_PLL2_100M_CLK:
- case SYSTEM_PLL2_50M_CLK:
- case SYSTEM_PLL3_CLK:
- return decode_sscg_pll(root_src);
- default:
- return 0;
- }
-
- return 0;
-}
-
-static u32 get_root_clk(enum clk_root_index clock_id)
-{
- enum clk_root_src root_src;
- u32 post_podf, pre_podf, root_src_clk;
-
- if (clock_root_enabled(clock_id) <= 0)
- return 0;
-
- if (clock_get_prediv(clock_id, &pre_podf) < 0)
- return 0;
-
- if (clock_get_postdiv(clock_id, &post_podf) < 0)
- return 0;
-
- if (clock_get_src(clock_id, &root_src) < 0)
- return 0;
-
- root_src_clk = get_root_src_clk(root_src);
-
- return root_src_clk / (post_podf + 1) / (pre_podf + 1);
-}
-
-#ifdef CONFIG_SECURE_BOOT
-void hab_caam_clock_enable(unsigned char enable)
-{
- /* The CAAM clock is always on for iMX8M */
-}
-#endif
-
-#ifdef CONFIG_MXC_OCOTP
-void enable_ocotp_clk(unsigned char enable)
-{
- clock_enable(CCGR_OCOTP, !!enable);
-}
-#endif
-
-int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
-{
- /* 0 - 3 is valid i2c num */
- if (i2c_num > 3)
- return -EINVAL;
-
- clock_enable(CCGR_I2C1 + i2c_num, !!enable);
-
- return 0;
-}
-
-unsigned int mxc_get_clock(enum clk_root_index clk)
-{
- u32 val;
-
- if (clk >= CLK_ROOT_MAX)
- return 0;
-
- if (clk == MXC_ARM_CLK)
- return get_root_clk(ARM_A53_CLK_ROOT);
-
- if (clk == MXC_IPG_CLK) {
- clock_get_target_val(IPG_CLK_ROOT, &val);
- val = val & 0x3;
- return get_root_clk(AHB_CLK_ROOT) / (val + 1);
- }
-
- return get_root_clk(clk);
-}
-
-u32 imx_get_uartclk(void)
-{
- return mxc_get_clock(UART1_CLK_ROOT);
-}
-
-void mxs_set_lcdclk(u32 base_addr, u32 freq)
-{
- /*
- * LCDIF_PIXEL_CLK: select 800MHz root clock,
- * select pre divider 8, output is 100 MHz
- */
- clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(4) |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
-}
-
-void init_wdog_clk(void)
-{
- clock_enable(CCGR_WDOG1, 0);
- clock_enable(CCGR_WDOG2, 0);
- clock_enable(CCGR_WDOG3, 0);
- clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_enable(CCGR_WDOG1, 1);
- clock_enable(CCGR_WDOG2, 1);
- clock_enable(CCGR_WDOG3, 1);
-}
-
-void init_usb_clk(void)
-{
- if (!is_usb_boot()) {
- clock_enable(CCGR_USB_CTRL1, 0);
- clock_enable(CCGR_USB_CTRL2, 0);
- clock_enable(CCGR_USB_PHY1, 0);
- clock_enable(CCGR_USB_PHY2, 0);
- /* 500MHz */
- clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
- /* 100MHz */
- clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
- /* 100MHz */
- clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
- clock_enable(CCGR_USB_CTRL1, 1);
- clock_enable(CCGR_USB_CTRL2, 1);
- clock_enable(CCGR_USB_PHY1, 1);
- clock_enable(CCGR_USB_PHY2, 1);
- }
-}
-
-void init_nand_clk(void)
-{
- /*
- * set rawnand root
- * sys pll1 400M
- */
- clock_enable(CCGR_RAWNAND, 0);
- clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
- clock_enable(CCGR_RAWNAND, 1);
-}
-
-void init_uart_clk(u32 index)
-{
- /* Set uart clock root 25M OSC */
- switch (index) {
- case 0:
- clock_enable(CCGR_UART1, 0);
- clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_enable(CCGR_UART1, 1);
- return;
- case 1:
- clock_enable(CCGR_UART2, 0);
- clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_enable(CCGR_UART2, 1);
- return;
- case 2:
- clock_enable(CCGR_UART3, 0);
- clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_enable(CCGR_UART3, 1);
- return;
- case 3:
- clock_enable(CCGR_UART4, 0);
- clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_enable(CCGR_UART4, 1);
- return;
- default:
- printf("Invalid uart index\n");
- return;
- }
-}
-
-void init_clk_usdhc(u32 index)
-{
- /*
- * set usdhc clock root
- * sys pll1 400M
- */
- switch (index) {
- case 0:
- clock_enable(CCGR_USDHC1, 0);
- clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
- clock_enable(CCGR_USDHC1, 1);
- return;
- case 1:
- clock_enable(CCGR_USDHC2, 0);
- clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
- clock_enable(CCGR_USDHC2, 1);
- return;
- default:
- printf("Invalid usdhc index\n");
- return;
- }
-}
-
-int set_clk_qspi(void)
-{
- /*
- * set qspi root
- * sys pll1 100M
- */
- clock_enable(CCGR_QSPI, 0);
- clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(7));
- clock_enable(CCGR_QSPI, 1);
-
- return 0;
-}
-
-#ifdef CONFIG_FEC_MXC
-int set_clk_enet(enum enet_freq type)
-{
- u32 target;
- u32 enet1_ref;
-
- switch (type) {
- case ENET_125MHZ:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
- break;
- case ENET_50MHZ:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
- break;
- case ENET_25MHZ:
- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
- break;
- default:
- return -EINVAL;
- }
-
- /* disable the clock first */
- clock_enable(CCGR_ENET1, 0);
- clock_enable(CCGR_SIM_ENET, 0);
-
- /* set enet axi clock 266Mhz */
- target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(ENET_AXI_CLK_ROOT, target);
-
- target = CLK_ROOT_ON | enet1_ref |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
- clock_set_target_val(ENET_REF_CLK_ROOT, target);
-
- target = CLK_ROOT_ON |
- ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
- clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
-
- /* enable clock */
- clock_enable(CCGR_SIM_ENET, 1);
- clock_enable(CCGR_ENET1, 1);
-
- return 0;
-}
-#endif
-
-u32 imx_get_fecclk(void)
-{
- return get_root_clk(ENET_AXI_CLK_ROOT);
-}
-
-static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
- DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
- CLK_ROOT_PRE_DIV2),
- DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
- CLK_ROOT_PRE_DIV2),
- DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
- CLK_ROOT_PRE_DIV2),
-};
-
-void dram_enable_bypass(ulong clk_val)
-{
- int i;
- struct dram_bypass_clk_setting *config;
-
- for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
- if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
- break;
- }
-
- if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
- printf("No matched freq table %lu\n", clk_val);
- return;
- }
-
- config = &imx8mq_dram_bypass_tbl[i];
-
- clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
- CLK_ROOT_PRE_DIV(config->alt_pre_div));
- clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
- CLK_ROOT_PRE_DIV(config->apb_pre_div));
- clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
-}
-
-void dram_disable_bypass(void)
-{
- clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
- clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(4) |
- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
-}
-
-#ifdef CONFIG_SPL_BUILD
-void dram_pll_init(ulong pll_val)
-{
- u32 val;
- void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
- void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
-
- /* Bypass */
- setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
- setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
-
- switch (pll_val) {
- case MHZ(800):
- val = readl(pll_cfg_reg2);
- val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
- SSCG_PLL_FEEDBACK_DIV_F2_MASK |
- SSCG_PLL_FEEDBACK_DIV_F1_MASK |
- SSCG_PLL_REF_DIVR2_MASK);
- val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
- val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
- val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
- val |= SSCG_PLL_REF_DIVR2_VAL(29);
- writel(val, pll_cfg_reg2);
- break;
- case MHZ(600):
- val = readl(pll_cfg_reg2);
- val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
- SSCG_PLL_FEEDBACK_DIV_F2_MASK |
- SSCG_PLL_FEEDBACK_DIV_F1_MASK |
- SSCG_PLL_REF_DIVR2_MASK);
- val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
- val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
- val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
- val |= SSCG_PLL_REF_DIVR2_VAL(29);
- writel(val, pll_cfg_reg2);
- break;
- case MHZ(400):
- val = readl(pll_cfg_reg2);
- val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
- SSCG_PLL_FEEDBACK_DIV_F2_MASK |
- SSCG_PLL_FEEDBACK_DIV_F1_MASK |
- SSCG_PLL_REF_DIVR2_MASK);
- val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
- val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
- val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
- val |= SSCG_PLL_REF_DIVR2_VAL(29);
- writel(val, pll_cfg_reg2);
- break;
- case MHZ(167):
- val = readl(pll_cfg_reg2);
- val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
- SSCG_PLL_FEEDBACK_DIV_F2_MASK |
- SSCG_PLL_FEEDBACK_DIV_F1_MASK |
- SSCG_PLL_REF_DIVR2_MASK);
- val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
- val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
- val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
- val |= SSCG_PLL_REF_DIVR2_VAL(30);
- writel(val, pll_cfg_reg2);
- break;
- default:
- break;
- }
-
- /* Clear power down bit */
- clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
- /* Eanble ARM_PLL/SYS_PLL */
- setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
-
- /* Clear bypass */
- clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
- __udelay(100);
- clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
- /* Wait lock */
- while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
- ;
-}
-
-int frac_pll_init(u32 pll, enum frac_pll_out_val val)
-{
- void __iomem *pll_cfg0, __iomem *pll_cfg1;
- u32 val_cfg0, val_cfg1;
- int ret;
-
- switch (pll) {
- case ANATOP_ARM_PLL:
- pll_cfg0 = &ana_pll->arm_pll_cfg0;
- pll_cfg1 = &ana_pll->arm_pll_cfg1;
-
- if (val == FRAC_PLL_OUT_1000M)
- val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
- else
- val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
- val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
- FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
- FRAC_PLL_REFCLK_DIV_VAL(4) |
- FRAC_PLL_OUTPUT_DIV_VAL(0);
- break;
- default:
- return -EINVAL;
- }
-
- /* bypass the clock */
- setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
- /* Set the value */
- writel(val_cfg1, pll_cfg1);
- writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
- val_cfg0 = readl(pll_cfg0);
- /* unbypass the clock */
- clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
- ret = readl_poll_timeout(pll_cfg0, val_cfg0,
- val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
- if (ret)
- printf("%s timeout\n", __func__);
- clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
-
- return 0;
-}
-
-int sscg_pll_init(u32 pll)
-{
- void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
- u32 val_cfg0, val_cfg1, val_cfg2, val;
- u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
- int ret;
-
- switch (pll) {
- case ANATOP_SYSTEM_PLL1:
- pll_cfg0 = &ana_pll->sys_pll1_cfg0;
- pll_cfg1 = &ana_pll->sys_pll1_cfg1;
- pll_cfg2 = &ana_pll->sys_pll1_cfg2;
- /* 800MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- case ANATOP_SYSTEM_PLL2:
- pll_cfg0 = &ana_pll->sys_pll2_cfg0;
- pll_cfg1 = &ana_pll->sys_pll2_cfg1;
- pll_cfg2 = &ana_pll->sys_pll2_cfg2;
- /* 1000MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
- SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
- SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
- SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
- SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- case ANATOP_SYSTEM_PLL3:
- pll_cfg0 = &ana_pll->sys_pll3_cfg0;
- pll_cfg1 = &ana_pll->sys_pll3_cfg1;
- pll_cfg2 = &ana_pll->sys_pll3_cfg2;
- /* 800MHz */
- val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
- SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
- val_cfg1 = 0;
- val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
- SSCG_PLL_REFCLK_SEL_OSC_25M;
- break;
- default:
- return -EINVAL;
- }
-
- /*bypass*/
- setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
- /* set value */
- writel(val_cfg2, pll_cfg2);
- writel(val_cfg1, pll_cfg1);
- /*unbypass1 and wait 70us */
- writel(val_cfg0 | bypass2_mask, pll_cfg1);
-
- __udelay(70);
-
- /* unbypass2 and wait lock */
- writel(val_cfg0, pll_cfg1);
- ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
- if (ret)
- printf("%s timeout\n", __func__);
-
- return ret;
-}
-
-int clock_init(void)
-{
- u32 grade;
-
- clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(0));
-
- /*
- * 8MQ only supports two grades: consumer and industrial.
- * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
- */
- grade = get_cpu_temp_grade(NULL, NULL);
- if (!grade) {
- frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
- clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
- } else {
- frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
- clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1) |
- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
- }
- /*
- * According to ANAMIX SPEC
- * sys pll1 fixed at 800MHz
- * sys pll2 fixed at 1GHz
- * Here we only enable the outputs.
- */
- setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
- SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
- SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
- SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
- SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
-
- setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
- SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
- SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
- SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
- SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
-
- clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
- CLK_ROOT_SOURCE_SEL(1));
-
- init_wdog_clk();
- clock_enable(CCGR_TSENSOR, 1);
-
- return 0;
-}
-#endif
-
-/*
- * Dump some clockes.
- */
-#ifndef CONFIG_SPL_BUILD
-int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 freq;
-
- freq = decode_frac_pll(ARM_PLL_CLK);
- printf("ARM_PLL %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
- printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
- printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
- printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
- printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
- printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
- printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
- printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
- printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
- printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
- printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
- printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
- printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
- printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
- printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
- printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
- printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
- printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
- printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
- freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
- printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
- freq = mxc_get_clock(UART1_CLK_ROOT);
- printf("UART1 %8d MHz\n", freq / 1000000);
- freq = mxc_get_clock(USDHC1_CLK_ROOT);
- printf("USDHC1 %8d MHz\n", freq / 1000000);
- freq = mxc_get_clock(QSPI_CLK_ROOT);
- printf("QSPI %8d MHz\n", freq / 1000000);
- return 0;
-}
-
-U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
- "display clocks",
- ""
-);
-#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <errno.h>
+#include <linux/iopoll.h>
+
+static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
+
+static u32 decode_frac_pll(enum clk_root_src frac_pll)
+{
+ u32 pll_cfg0, pll_cfg1, pllout;
+ u32 pll_refclk_sel, pll_refclk;
+ u32 divr_val, divq_val, divf_val, divff, divfi;
+ u32 pllout_div_shift, pllout_div_mask, pllout_div;
+
+ switch (frac_pll) {
+ case ARM_PLL_CLK:
+ pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
+ pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
+ pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
+ pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
+ break;
+ default:
+ printf("Frac PLL %d not supporte\n", frac_pll);
+ return 0;
+ }
+
+ pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
+ pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
+
+ /* Power down */
+ if (pll_cfg0 & FRAC_PLL_PD_MASK)
+ return 0;
+
+ /* output not enabled */
+ if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
+ return 0;
+
+ pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
+
+ if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
+ pll_refclk = 25000000u;
+ else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
+ pll_refclk = 27000000u;
+ else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
+ pll_refclk = 27000000u;
+ else
+ pll_refclk = 0;
+
+ if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
+ return pll_refclk;
+
+ divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
+ FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
+ divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
+
+ divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
+ FRAC_PLL_FRAC_DIV_CTL_SHIFT;
+ divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
+
+ divf_val = 1 + divfi + divff / (1 << 24);
+
+ pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
+ ((divq_val + 1) * 2);
+
+ return pllout / (pllout_div + 1);
+}
+
+static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
+{
+ u32 pll_cfg0, pll_cfg1, pll_cfg2;
+ u32 pll_refclk_sel, pll_refclk;
+ u32 divr1, divr2, divf1, divf2, divq, div;
+ u32 sse;
+ u32 pll_clke;
+ u32 pllout_div_shift, pllout_div_mask, pllout_div;
+ u32 pllout;
+
+ switch (sscg_pll) {
+ case SYSTEM_PLL1_800M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
+ pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
+ pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
+ pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
+ break;
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL2_50M_CLK:
+ pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
+ pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
+ pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
+ pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
+ break;
+ case SYSTEM_PLL3_CLK:
+ pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
+ pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
+ pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
+ pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
+ break;
+ case DRAM_PLL1_CLK:
+ pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
+ pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
+ pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
+ pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
+ pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
+ break;
+ default:
+ printf("sscg pll %d not supporte\n", sscg_pll);
+ return 0;
+ }
+
+ switch (sscg_pll) {
+ case DRAM_PLL1_CLK:
+ pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
+ div = 1;
+ break;
+ case SYSTEM_PLL3_CLK:
+ pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
+ div = 1;
+ break;
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL1_800M_CLK:
+ pll_clke = SSCG_PLL_CLKE_MASK;
+ div = 1;
+ break;
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
+ div = 2;
+ break;
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
+ div = 3;
+ break;
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
+ div = 4;
+ break;
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
+ div = 5;
+ break;
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
+ div = 6;
+ break;
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
+ div = 8;
+ break;
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
+ div = 10;
+ break;
+ case SYSTEM_PLL2_50M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
+ div = 20;
+ break;
+ default:
+ printf("sscg pll %d not supporte\n", sscg_pll);
+ return 0;
+ }
+
+ /* Power down */
+ if (pll_cfg0 & SSCG_PLL_PD_MASK)
+ return 0;
+
+ /* output not enabled */
+ if ((pll_cfg0 & pll_clke) == 0)
+ return 0;
+
+ pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
+ pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
+
+ pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
+
+ if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
+ pll_refclk = 25000000u;
+ else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
+ pll_refclk = 27000000u;
+ else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
+ pll_refclk = 27000000u;
+ else
+ pll_refclk = 0;
+
+ /* We assume bypass1/2 are the same value */
+ if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
+ (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
+ return pll_refclk;
+
+ divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
+ SSCG_PLL_REF_DIVR1_SHIFT;
+ divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
+ SSCG_PLL_REF_DIVR2_SHIFT;
+ divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
+ SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
+ divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
+ SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
+ divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
+ SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
+ sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
+
+ if (sse)
+ sse = 8;
+ else
+ sse = 2;
+
+ pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
+ (divr2 + 1) * (divf2 + 1) / (divq + 1);
+
+ return pllout / (pllout_div + 1) / div;
+}
+
+static u32 get_root_src_clk(enum clk_root_src root_src)
+{
+ switch (root_src) {
+ case OSC_25M_CLK:
+ return 25000000;
+ case OSC_27M_CLK:
+ return 27000000;
+ case OSC_32K_CLK:
+ return 32768;
+ case ARM_PLL_CLK:
+ return decode_frac_pll(root_src);
+ case SYSTEM_PLL1_800M_CLK:
+ case SYSTEM_PLL1_400M_CLK:
+ case SYSTEM_PLL1_266M_CLK:
+ case SYSTEM_PLL1_200M_CLK:
+ case SYSTEM_PLL1_160M_CLK:
+ case SYSTEM_PLL1_133M_CLK:
+ case SYSTEM_PLL1_100M_CLK:
+ case SYSTEM_PLL1_80M_CLK:
+ case SYSTEM_PLL1_40M_CLK:
+ case SYSTEM_PLL2_1000M_CLK:
+ case SYSTEM_PLL2_500M_CLK:
+ case SYSTEM_PLL2_333M_CLK:
+ case SYSTEM_PLL2_250M_CLK:
+ case SYSTEM_PLL2_200M_CLK:
+ case SYSTEM_PLL2_166M_CLK:
+ case SYSTEM_PLL2_125M_CLK:
+ case SYSTEM_PLL2_100M_CLK:
+ case SYSTEM_PLL2_50M_CLK:
+ case SYSTEM_PLL3_CLK:
+ return decode_sscg_pll(root_src);
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+static u32 get_root_clk(enum clk_root_index clock_id)
+{
+ enum clk_root_src root_src;
+ u32 post_podf, pre_podf, root_src_clk;
+
+ if (clock_root_enabled(clock_id) <= 0)
+ return 0;
+
+ if (clock_get_prediv(clock_id, &pre_podf) < 0)
+ return 0;
+
+ if (clock_get_postdiv(clock_id, &post_podf) < 0)
+ return 0;
+
+ if (clock_get_src(clock_id, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ return root_src_clk / (post_podf + 1) / (pre_podf + 1);
+}
+
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+ /* The CAAM clock is always on for iMX8M */
+}
+#endif
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ clock_enable(CCGR_OCOTP, !!enable);
+}
+#endif
+
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
+{
+ /* 0 - 3 is valid i2c num */
+ if (i2c_num > 3)
+ return -EINVAL;
+
+ clock_enable(CCGR_I2C1 + i2c_num, !!enable);
+
+ return 0;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ u32 val;
+
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_root_clk(ARM_A53_CLK_ROOT);
+ case MXC_IPG_CLK:
+ clock_get_target_val(IPG_CLK_ROOT, &val);
+ val = val & 0x3;
+ return get_root_clk(AHB_CLK_ROOT) / (val + 1);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
+ case MXC_ESDHC_CLK:
+ return get_root_clk(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_QSPI_CLK:
+ return get_root_clk(QSPI_CLK_ROOT);
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return mxc_get_clock(MXC_UART_CLK);
+}
+
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
+{
+ /*
+ * LCDIF_PIXEL_CLK: select 800MHz root clock,
+ * select pre divider 8, output is 100 MHz
+ */
+ clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(4) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
+}
+
+void init_wdog_clk(void)
+{
+ clock_enable(CCGR_WDOG1, 0);
+ clock_enable(CCGR_WDOG2, 0);
+ clock_enable(CCGR_WDOG3, 0);
+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_WDOG1, 1);
+ clock_enable(CCGR_WDOG2, 1);
+ clock_enable(CCGR_WDOG3, 1);
+}
+
+void init_usb_clk(void)
+{
+ if (!is_usb_boot()) {
+ clock_enable(CCGR_USB_CTRL1, 0);
+ clock_enable(CCGR_USB_CTRL2, 0);
+ clock_enable(CCGR_USB_PHY1, 0);
+ clock_enable(CCGR_USB_PHY2, 0);
+ /* 500MHz */
+ clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ /* 100MHz */
+ clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ /* 100MHz */
+ clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_USB_CTRL1, 1);
+ clock_enable(CCGR_USB_CTRL2, 1);
+ clock_enable(CCGR_USB_PHY1, 1);
+ clock_enable(CCGR_USB_PHY2, 1);
+ }
+}
+
+void init_nand_clk(void)
+{
+ /*
+ * set rawnand root
+ * sys pll1 400M
+ */
+ clock_enable(CCGR_RAWNAND, 0);
+ clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
+ clock_enable(CCGR_RAWNAND, 1);
+}
+
+void init_uart_clk(u32 index)
+{
+ /* Set uart clock root 25M OSC */
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_UART1, 0);
+ clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_UART2, 0);
+ clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART2, 1);
+ return;
+ case 2:
+ clock_enable(CCGR_UART3, 0);
+ clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART3, 1);
+ return;
+ case 3:
+ clock_enable(CCGR_UART4, 0);
+ clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_enable(CCGR_UART4, 1);
+ return;
+ default:
+ printf("Invalid uart index\n");
+ return;
+ }
+}
+
+void init_clk_usdhc(u32 index)
+{
+ /*
+ * set usdhc clock root
+ * sys pll1 400M
+ */
+ switch (index) {
+ case 0:
+ clock_enable(CCGR_USDHC1, 0);
+ clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ clock_enable(CCGR_USDHC1, 1);
+ return;
+ case 1:
+ clock_enable(CCGR_USDHC2, 0);
+ clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ clock_enable(CCGR_USDHC2, 1);
+ return;
+ default:
+ printf("Invalid usdhc index\n");
+ return;
+ }
+}
+
+int set_clk_qspi(void)
+{
+ /*
+ * set qspi root
+ * sys pll1 100M
+ */
+ clock_enable(CCGR_QSPI, 0);
+ clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(7));
+ clock_enable(CCGR_QSPI, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ u32 enet1_ref;
+
+ switch (type) {
+ case ENET_125MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHZ:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_SIM_ENET, 0);
+
+ /* set enet axi clock 266Mhz */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON |
+ ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+ /* enable clock */
+ clock_enable(CCGR_SIM_ENET, 1);
+ clock_enable(CCGR_ENET1, 1);
+
+ return 0;
+}
+#endif
+
+u32 imx_get_fecclk(void)
+{
+ return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
+ DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
+ CLK_ROOT_PRE_DIV2),
+ DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
+ CLK_ROOT_PRE_DIV2),
+ DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
+ CLK_ROOT_PRE_DIV2),
+};
+
+void dram_enable_bypass(ulong clk_val)
+{
+ int i;
+ struct dram_bypass_clk_setting *config;
+
+ for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
+ if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
+ printf("No matched freq table %lu\n", clk_val);
+ return;
+ }
+
+ config = &imx8mq_dram_bypass_tbl[i];
+
+ clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
+ CLK_ROOT_PRE_DIV(config->alt_pre_div));
+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
+ CLK_ROOT_PRE_DIV(config->apb_pre_div));
+ clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+}
+
+void dram_disable_bypass(void)
+{
+ clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(4) |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+ u32 val;
+ void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
+ void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
+
+ /* Bypass */
+ setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
+ setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
+
+ switch (pll_val) {
+ case MHZ(800):
+ val = readl(pll_cfg_reg2);
+ val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+ SSCG_PLL_REF_DIVR2_MASK);
+ val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
+ val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
+ val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+ val |= SSCG_PLL_REF_DIVR2_VAL(29);
+ writel(val, pll_cfg_reg2);
+ break;
+ case MHZ(600):
+ val = readl(pll_cfg_reg2);
+ val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+ SSCG_PLL_REF_DIVR2_MASK);
+ val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
+ val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
+ val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+ val |= SSCG_PLL_REF_DIVR2_VAL(29);
+ writel(val, pll_cfg_reg2);
+ break;
+ case MHZ(400):
+ val = readl(pll_cfg_reg2);
+ val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+ SSCG_PLL_REF_DIVR2_MASK);
+ val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
+ val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
+ val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
+ val |= SSCG_PLL_REF_DIVR2_VAL(29);
+ writel(val, pll_cfg_reg2);
+ break;
+ case MHZ(167):
+ val = readl(pll_cfg_reg2);
+ val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK |
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK |
+ SSCG_PLL_REF_DIVR2_MASK);
+ val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
+ val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
+ val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
+ val |= SSCG_PLL_REF_DIVR2_VAL(30);
+ writel(val, pll_cfg_reg2);
+ break;
+ default:
+ break;
+ }
+
+ /* Clear power down bit */
+ clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
+ /* Eanble ARM_PLL/SYS_PLL */
+ setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
+
+ /* Clear bypass */
+ clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
+ __udelay(100);
+ clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
+ /* Wait lock */
+ while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
+ ;
+}
+
+int frac_pll_init(u32 pll, enum frac_pll_out_val val)
+{
+ void __iomem *pll_cfg0, __iomem *pll_cfg1;
+ u32 val_cfg0, val_cfg1;
+ int ret;
+
+ switch (pll) {
+ case ANATOP_ARM_PLL:
+ pll_cfg0 = &ana_pll->arm_pll_cfg0;
+ pll_cfg1 = &ana_pll->arm_pll_cfg1;
+
+ if (val == FRAC_PLL_OUT_1000M)
+ val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
+ else
+ val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
+ val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
+ FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
+ FRAC_PLL_REFCLK_DIV_VAL(4) |
+ FRAC_PLL_OUTPUT_DIV_VAL(0);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* bypass the clock */
+ setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+ /* Set the value */
+ writel(val_cfg1, pll_cfg1);
+ writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
+ val_cfg0 = readl(pll_cfg0);
+ /* unbypass the clock */
+ clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
+ ret = readl_poll_timeout(pll_cfg0, val_cfg0,
+ val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
+ if (ret)
+ printf("%s timeout\n", __func__);
+ clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
+
+ return 0;
+}
+
+int sscg_pll_init(u32 pll)
+{
+ void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
+ u32 val_cfg0, val_cfg1, val_cfg2, val;
+ u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
+ int ret;
+
+ switch (pll) {
+ case ANATOP_SYSTEM_PLL1:
+ pll_cfg0 = &ana_pll->sys_pll1_cfg0;
+ pll_cfg1 = &ana_pll->sys_pll1_cfg1;
+ pll_cfg2 = &ana_pll->sys_pll1_cfg2;
+ /* 800MHz */
+ val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+ SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+ val_cfg1 = 0;
+ val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+ SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+ SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+ SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+ SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+ SSCG_PLL_REFCLK_SEL_OSC_25M;
+ break;
+ case ANATOP_SYSTEM_PLL2:
+ pll_cfg0 = &ana_pll->sys_pll2_cfg0;
+ pll_cfg1 = &ana_pll->sys_pll2_cfg1;
+ pll_cfg2 = &ana_pll->sys_pll2_cfg2;
+ /* 1000MHz */
+ val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+ SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
+ val_cfg1 = 0;
+ val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+ SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+ SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+ SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+ SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+ SSCG_PLL_REFCLK_SEL_OSC_25M;
+ break;
+ case ANATOP_SYSTEM_PLL3:
+ pll_cfg0 = &ana_pll->sys_pll3_cfg0;
+ pll_cfg1 = &ana_pll->sys_pll3_cfg1;
+ pll_cfg2 = &ana_pll->sys_pll3_cfg2;
+ /* 800MHz */
+ val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+ SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+ val_cfg1 = 0;
+ val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+ SSCG_PLL_REFCLK_SEL_OSC_25M;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*bypass*/
+ setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
+ /* set value */
+ writel(val_cfg2, pll_cfg2);
+ writel(val_cfg1, pll_cfg1);
+ /*unbypass1 and wait 70us */
+ writel(val_cfg0 | bypass2_mask, pll_cfg1);
+
+ __udelay(70);
+
+ /* unbypass2 and wait lock */
+ writel(val_cfg0, pll_cfg1);
+ ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
+ if (ret)
+ printf("%s timeout\n", __func__);
+
+ return ret;
+}
+
+int clock_init(void)
+{
+ u32 grade;
+
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(0));
+
+ /*
+ * 8MQ only supports two grades: consumer and industrial.
+ * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
+ */
+ grade = get_cpu_temp_grade(NULL, NULL);
+ if (!grade) {
+ frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
+ } else {
+ frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
+ clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
+ }
+ /*
+ * According to ANAMIX SPEC
+ * sys pll1 fixed at 800MHz
+ * sys pll2 fixed at 1GHz
+ * Here we only enable the outputs.
+ */
+ setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
+ SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
+ SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
+ SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
+ SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
+
+ setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
+ SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
+ SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
+ SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
+ SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
+
+ clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+
+ init_wdog_clk();
+ clock_enable(CCGR_TSENSOR, 1);
+
+ return 0;
+}
+#endif
+
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 freq;
+
+ freq = decode_frac_pll(ARM_PLL_CLK);
+ printf("ARM_PLL %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
+ printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
+ printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
+ printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
+ printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
+ printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
+ printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
+ printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
+ printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
+ printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
+ printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
+ printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
+ printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
+ printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
+ printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
+ printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
+ printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
+ printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
+ printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
+ freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
+ printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_UART_CLK);
+ printf("UART1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_ESDHC_CLK);
+ printf("USDHC1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_QSPI_CLK);
+ printf("QSPI %8d MHz\n", freq / 1000000);
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
+ "display clocks",
+ ""
+);
+#endif
switch (i) {
case 0:
init_clk_usdhc(0);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
break;
case 1:
init_clk_usdhc(1);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
switch (i) {
case 0:
init_clk_usdhc(0);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
break;
case 1:
init_clk_usdhc(1);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
ARRAY_SIZE(usdhc2_pads));
gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
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