MLK-13910: ARM: imx7d: clk: correct enet clock CCGR register offset

Correct enet clock CCGR register offset.

CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK

IMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.

IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.

Update copyright information.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>

diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index eaf697a..c8f75bc 100644 (file)
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -1,6 +1,7 @@
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
  * Copyright 2016 Toradex AG
+ * Copyright 2017 NXP.
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -392,11 +393,11 @@
                interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                        <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
                        <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+               clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
                        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
                        <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
                        <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
-                       <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+                       <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
                clock-names = "ipg", "ahb", "ptp",
                        "enet_clk_ref", "enet_out";
                fsl,num-tx-queues=<3>;

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index ae28741..47da8b6 100644 (file)
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -1021,11 +1021,11 @@
                                interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                               clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
                                        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
                                        <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
                                        <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
-                                       <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+                                       <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
                                clock-names = "ipg", "ahb", "ptp",
                                        "enet_clk_ref", "enet_out";
                                fsl,num-tx-queues=<3>;

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 3cb471b..7c977fe 100644 (file)
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -27,6 +28,8 @@ static u32 share_count_sai1;
 static u32 share_count_sai2;
 static u32 share_count_sai3;
 static u32 share_count_pxp;
+static u32 share_count_enet1;
+static u32 share_count_enet2;
 
 static struct clk_div_table test_div_table[] = {
        { .val = 3, .div = 1, },
@@ -817,6 +820,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
        clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
        clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
+       clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1);
+       clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1);
+       clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2);
+       clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2);
        clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1);
        clks[IMX7D_SAI1_IPG_CLK]  = imx_clk_gate2_shared2("sai1_ipg_clk",  "ipg_root_clk",  base + 0x48c0, 0, &share_count_sai1);
        clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2);
@@ -824,11 +831,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3);
        clks[IMX7D_SAI3_IPG_CLK]  = imx_clk_gate2_shared2("sai3_ipg_clk",  "ipg_root_clk",  base + 0x48e0, 0, &share_count_sai3);
        clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
-       clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
-       clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
-       clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
-       clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);
-       clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
        clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
        clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate2_flags("nand_root_clk", "nand_post_div", base + 0x4140, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
        clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0);

diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index 4fce064..0afab1b 100644 (file)
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -453,6 +454,8 @@
 #define IMX7D_CAAM_CLK                         440
 #define IMX7D_PXP_IPG_CLK              441
 #define IMX7D_PXP_AXI_CLK              442
-#define IMX7D_CLK_END                  443
+#define IMX7D_ENET1_IPG_ROOT_CLK        443
+#define IMX7D_ENET2_IPG_ROOT_CLK        444
+#define IMX7D_CLK_END                  445
 
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */