SSI-73: arm64: dts: imx8mn: add crypto support

Add crypto, caam_sm, caam_snvs and caam_secvio nodes in device
tree for CAAM, secure memory support and security violation reports.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi
index df72f3c..f64807e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi
@@ -721,6 +721,52 @@
                status = "disabled";
        };
 
+       crypto: caam@30900000 {
+               compatible = "fsl,sec-v4.0";
+               #address-cells = <0x1>;
+               #size-cells = <0x1>;
+               reg = <0 0x30900000 0 0x40000>;
+               ranges = <0 0 0x30900000 0x40000>;
+               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+
+               sec_jr0: jr0@1000 {
+                        compatible = "fsl,sec-v4.0-job-ring";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr1: jr1@2000 {
+                        compatible = "fsl,sec-v4.0-job-ring";
+                        reg = <0x2000 0x1000>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr2: jr2@3000 {
+                        compatible = "fsl,sec-v4.0-job-ring";
+                        reg = <0x3000 0x1000>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+               };
+       };
+
+       caam_sm: caam-sm@00100000 {
+               compatible = "fsl,imx6q-caam-sm";
+               reg = <0 0x00100000 0 0x8000>;
+       };
+
+       caam_snvs: caam-snvs@30370000 {
+               compatible = "fsl,imx6q-caam-snvs";
+               reg = <0 0x30370000 0 0x10000>;
+       };
+
+       irq_sec_vio: caam_secvio {
+               compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               jtag-tamper = "disabled";
+               watchdog-tamper = "enabled";
+               internal-boot-tamper = "enabled";
+               external-pin-tamper = "disabled";
+       };
+
        i2c1: i2c@30a20000 {
                #address-cells = <1>;
                #size-cells = <0>;