MLK-11087: mtd:qspi: support DDR Quad mode for Macronix mx25l51245g

Enable DDR quad mode for Macronix qspi chip mx25l51245g by setting Quad
bit in status register and enabling in dts file.

The LUT for SPINOR_OP_READ_1_4_4_D was initially designed for Spansion
qspi chip, so there is one cycle for "mode" after address and before
dummy. While Macronix qspi chip doesn't have this feature, so we just
take off one cycle in dts file to bypass this problem.

Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked and merge from commit e03fdad1c7713a7db70112e00c4ae96848accd34)

diff --git a/arch/arm/boot/dts/imx7d-sdb-qspi.dts b/arch/arm/boot/dts/imx7d-sdb-qspi.dts
index 83b0401..d49ddf2 100644 (file)
--- a/arch/arm/boot/dts/imx7d-sdb-qspi.dts
+++ b/arch/arm/boot/dts/imx7d-sdb-qspi.dts
@@ -39,6 +39,8 @@
                #size-cells = <1>;
                compatible = "macronix,mx25l51245g";
                spi-max-frequency = <29000000>;
+               /* take off one dummy cycle */
+               spi-nor,ddr-quad-read-dummy = <5>;
                reg = <0>;
        };
 };

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 83cd243..bde7bda 100644 (file)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1303,6 +1303,14 @@ static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
                        return status;
                }
                return status;
+       case CFI_MFR_MACRONIX:
+               status = macronix_quad_enable(nor);
+               if (status) {
+                       dev_err(nor->dev,
+                               "Macronix DDR quad-read not enabled\n");
+                       return status;
+               }
+               return status;
        case CFI_MFR_ST: /* Micron, actually */
                /* DTR quad read works with the Extended SPI protocol. */
                return 0;
@@ -1505,6 +1513,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
                        nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
                } else if (JEDEC_MFR(info) == CFI_MFR_ST) {
                        nor->read_opcode = SPINOR_OP_READ_1_1_4_D;
+               } else if (JEDEC_MFR(info) == CFI_MFR_MACRONIX) {
+                       nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
                } else {
                        dev_err(dev, "DDR Quad Read is not supported.\n");
                        return -EINVAL;