MLK-23668-1 arm64: dts: imx8qm: add multi-pcie ports support

- Enable the PCIEB port on the i.MX8QM MEK and base board.
- In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory
required by PCIEB. Otherwise PCIEB can't link up when exist from
L2 mode when only PCIEB is used.
- PCIEB has one more PER clock, since that the PCIEA CSR register
would be configuired when PCIEB is initialized.
- Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index b9e0e35..916b18b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -94,7 +94,7 @@ hsio_subsys: bus@5f000000 {
                compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
                reg = <0x5f010000 0x10000>, /* Controller reg */
                      <0x7ff00000 0x80000>, /* PCI cfg space */
-                     <0x5f110000 0x60000>; /* lpcg, csr, msic, gpio */
+                     <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
                reg-names = "dbi", "config", "hsio";
                #address-cells = <3>;
                #size-cells = <2>;
@@ -113,17 +113,6 @@ hsio_subsys: bus@5f000000 {
                                 <0 0 0 2 &gic 0 106 4>,
                                 <0 0 0 3 &gic 0 107 4>,
                                 <0 0 0 4 &gic 0 108 4>;
-               /*
-                * Set the clks/pds for imx8qxp in default, clks/pds should be
-                * refined for exact hw design of imx8 pcie.
-                For example, when hsio-cfg = <PCIEAX1PCIEBX1SATA>,
-                set clks below.
-                       clocks = <&hsio_lpcg IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
-                               <&hsio_lpcg IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
-                               <&hsio_lpcg IMX8QM_HSIO_PHY_X2_PCLK_1>,
-                               <&hsio_lpcg IMX8QM_HSIO_PCIE_X1_PER_CLK>,
-                               <&hsio_lpcg IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>;
-                */
                clocks = <&pcieb_lpcg 0>,
                         <&pcieb_lpcg 1>,
                         <&pcieb_lpcg 2>,
@@ -132,7 +121,7 @@ hsio_subsys: bus@5f000000 {
                         <&pcieb_crr3_lpcg 0>,
                         <&misc_crr5_lpcg 0>;
                clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
-                             "pcie_phy", "phy_per","pcie_per", "misc_per";
+                             "pcie_phy", "phy_per", "pcie_per", "misc_per";
                power-domains = <&pd IMX_SC_R_PCIE_B>,
                                <&pd IMX_SC_R_SERDES_1>,
                                <&pd IMX_SC_R_HSIO_GPIO>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index dd3fe5d..9038720 100755 (executable)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -869,6 +869,14 @@
        status = "okay";
 };
 
+&pcieb{
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcieb>;
+       reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
+       ext_osc = <1>;
+       status = "okay";
+};
+
 &rpmsg0{
        /*
         * 64K for one rpmsg instance:
@@ -891,7 +899,7 @@
 
 &sata {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_pcieb>;
+       pinctrl-0 = <&pinctrl_sata>;
        clkreq-gpio = <&lsio_gpio4 30 GPIO_ACTIVE_LOW>;
        ext_osc = <1>;
        status = "okay";
@@ -1470,13 +1478,19 @@
        pinctrl_pciea: pcieagrp{
                fsl,pins = <
                        IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28                0x04000021
-                       IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27              0x06000021
                        IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29               0x06000021
                        IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09                   0x06000021
                >;
        };
 
        pinctrl_pcieb: pciebgrp{
+               fsl,pins = <
+                       IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31                0x04000021
+                       IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00               0x06000021
+               >;
+       };
+
+       pinctrl_sata: satagrp{
                fsl,pins = <
                        IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30              0x06000021
                >;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index b648374..e62957d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -35,10 +35,13 @@
                compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5f080000 0x10000>;
                #clock-cells = <1>;
-               clocks = <&hsio_refa_clk>, <&hsio_per_clk>;
-               bit-offset = <0 4>;
+               clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
+                       <&hsio_refa_clk>, <&hsio_per_clk>;
+               bit-offset = <0 4 16 20>;
                clock-output-names = "hsio_phyx2_pclk_0",
-                                    "hsio_phyx2_pclk_1";
+                                    "hsio_phyx2_pclk_1",
+                                    "hsio_phyx2_apbclk_0",
+                                    "hsio_phyx2_apbclk_1";
                power-domains = <&pd IMX_SC_R_SERDES_0>;
        };
 
@@ -90,7 +93,7 @@
                compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
                reg = <0x5f000000 0x10000>, /* Controller reg */
                      <0x6ff00000 0x80000>, /* PCI cfg space */
-                     <0x5f110000 0x60000>; /* lpcg, csr, msic, gpio */
+                     <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
                reg-names = "dbi", "config", "hsio";
                #address-cells = <3>;
                #size-cells = <2>;
@@ -121,7 +124,7 @@
                         <&pciea_crr2_lpcg 0>,
                         <&misc_crr5_lpcg 0>;
                clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
-                             "pcie_phy", "phy_per","pcie_per", "misc_per";
+                             "pcie_phy", "phy_per", "pcie_per", "misc_per";
                power-domains = <&pd IMX_SC_R_PCIE_A>,
                                <&pd IMX_SC_R_SERDES_0>,
                                <&pd IMX_SC_R_HSIO_GPIO>;
@@ -132,6 +135,53 @@
                status = "disabled";
        };
 
+       pcieb: pcie@0x5f010000 {
+               compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+               reg = <0x5f010000 0x10000>, /* Controller reg */
+                     <0x7ff00000 0x80000>, /* PCI cfg space */
+                     <0x5f080000 0xf0000>; /* lpcg, csr, msic, gpio */
+               reg-names = "dbi", "config", "hsio";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               device_type = "pci";
+               bus-range = <0x00 0xff>;
+               ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */
+                         0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
+               num-lanes = <1>;
+               num-viewport = <4>;
+               interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+               interrupt-names = "msi", "dma";
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0x7>;
+               interrupt-map =  <0 0 0 1 &gic 0 105 4>,
+                                <0 0 0 2 &gic 0 106 4>,
+                                <0 0 0 3 &gic 0 107 4>,
+                                <0 0 0 4 &gic 0 108 4>;
+               clocks = <&pcieb_lpcg 0>,
+                        <&pcieb_lpcg 1>,
+                        <&pcieb_lpcg 2>,
+                        <&phyx2_lpcg 1>,
+                        <&phyx2_lpcg 0>,
+                        <&phyx2_crr0_lpcg 0>,
+                        <&pcieb_crr3_lpcg 0>,
+                        <&pciea_crr2_lpcg 0>,
+                        <&misc_crr5_lpcg 0>;
+               clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+                             "pcie_phy", "pcie_phy_pclk", "phy_per",
+                             "pcie_per", "pciex2_per", "misc_per";
+               power-domains = <&pd IMX_SC_R_PCIE_B>,
+                               <&pd IMX_SC_R_PCIE_A>,
+                               <&pd IMX_SC_R_SERDES_0>,
+                               <&pd IMX_SC_R_HSIO_GPIO>;
+               power-domain-names = "pcie", "pcie_per", "pcie_phy",
+                                    "hsio_gpio";
+               fsl,max-link-speed = <3>;
+               hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+               local-addr = <0x80000000>;
+               status = "disabled";
+       };
+
        sata: sata@5f020000 {
                compatible = "fsl,imx8qm-ahci";
                reg = <0x5f020000 0x10000>, /* Controller reg */