arm64: dts: imx8mq: add inmate/root dts

Add inmate/root dts for jailhouse dual linux case.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 4d9785a..73bd84c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-ak4497.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-root.dtb imx8mq-evk-inmate.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-lcdif-rm67191.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts
new file mode 100644 (file)
index 0000000..f6e0694
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-inmate.dts
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+       model = "Freescale i.MX8MQ EVK";
+       compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+       interrupt-parent = <&gic>;
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+               clock-frequency = <8333333>;
+       };
+
+       clk_dummy: clock@7 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+               clock-output-names = "clk_dummy";
+       };
+
+       /* The clocks are configured by 1st OS */
+       clk_400m: clock@8 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <400000000>;
+               clock-output-names = "400m";
+       };
+       clk_266m: clock@9 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <266000000>;
+               clock-output-names = "266m";
+       };
+       clk_80m: clock@10 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <80000000>;
+               clock-output-names = "80m";
+       };
+
+       pci@bfb00000 {
+               compatible = "pci-host-ecam-generic";
+               device_type = "pci";
+               bus-range = <0 0>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 7>;
+               interrupt-map = <0 0 0 1 &gic GIC_SPI 109 IRQ_TYPE_EDGE_RISING>;
+               reg = <0x0 0xbfb00000 0x0 0x100000>;
+               ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
+       };
+};
+
+&clk {
+       /delete-property/ compatible;
+};
+
+/delete-node/ &{/cpus/cpu@0};
+/delete-node/ &{/cpus/cpu@1};
+/delete-node/ &{/pmu};
+
+&{/busfreq} {
+       status = "disabled";
+};
+
+&pgc_mipi {
+       status = "disabled";
+};
+
+&pgc_pcie {
+       status = "disabled";
+};
+
+&pgc_otg1 {
+       status = "disabled";
+};
+
+&pgc_otg2 {
+       status = "disabled";
+};
+
+&pgc_ddr1 {
+       status = "disabled";
+};
+
+&pgc_gpu {
+       status = "disabled";
+};
+
+&pgc_vpu {
+       status = "disabled";
+};
+
+&pgc_disp {
+       status = "disabled";
+};
+
+&pgc_mipi_csi1 {
+       status = "disabled";
+};
+
+&pgc_mipi_csi2 {
+       status = "disabled";
+};
+
+&pgc_pcie2 {
+       status = "disabled";
+};
+
+&gpio1 {
+       status = "disabled";
+};
+
+&gpio2 {
+       status = "disabled";
+};
+
+&gpio3 {
+       status = "disabled";
+};
+
+&gpio4 {
+       status = "disabled";
+};
+
+&gpio5 {
+       status = "disabled";
+};
+
+/delete-node/ &tmu;
+/delete-node/ &{/thermal-zones};
+
+/delete-node/ &irqsteer;
+&ocotp {
+       /* not let imx8_soc_init hang system */
+       /delete-property/ compatible;
+       status = "disabled";
+};
+/delete-node/ &snvs;
+
+&src {
+       /delete-property/ compatible;
+};
+
+&dcss {
+       /delete-property/ interrupt-parent;
+       /delete-property/ interrupts;
+       /delete-property/ interrupt-names;
+};
+
+&gpc {
+       status = "disabled";
+};
+
+/delete-node/ &system_counter;
+/*/delete-node/ &imx_ion;*/
+/delete-node/ &pcie0;
+/delete-node/ &pcie1;
+/delete-node/ &vpu;
+/delete-node/ &{/soc@0/ddr-pmu@3d800000};
+/delete-node/ &rpmsg;
+/delete-node/ &crypto;
+/*/delete-node/ &caam_sm;*/
+/*/delete-node/ &caam_snvs;*/
+/*/delete-node/ &irq_sec_vio;*/
+/*/delete-node/ &dma_apbh;*/
+/*/delete-node/ &gpmi;*/
+
+&iomuxc {
+       status = "disabled";
+};
+
+&iomuxc_gpr {
+       status = "disabled";
+};
+
+&mu {
+       status = "disabled";
+};
+
+&anatop {
+       status = "disabled";
+};
+
+&sdma2 {
+       status = "disabled";
+};
+
+&sdma1 {
+       status = "disabled";
+};
+
+&hdmi {
+       status = "disabled";
+};
+
+&uart2 {
+       clocks = <&osc_25m>,
+               <&osc_25m>;
+       clock-names = "ipg", "per";
+       /delete-property/ dmas;
+       /delete-property/ dmas-names;
+       status = "okay";
+};
+
+&usdhc1 {
+       clocks = <&clk_dummy>,
+               <&clk_266m>,
+               <&clk_400m>;
+       /delete-property/assigned-clocks;
+       /delete-property/assigned-clock-rates;
+       clock-names = "ipg", "ahb", "per";
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts
new file mode 100644 (file)
index 0000000..2d317bf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk-root.dts
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8mq-evk.dts"
+
+/ {
+       interrupt-parent = <&gic>;
+};
+
+&CPU_SLEEP {
+       /* We are not using GPC for now, need set 0 to avoid hang */
+       arm,psci-suspend-param = <0x0>;
+};
+
+&clk {
+       init-on-array = <IMX8MQ_CLK_UART2_ROOT
+                        IMX8MQ_CLK_UART2
+                        IMX8MQ_CLK_NAND_USDHC_BUS>;
+};
+
+&iomuxc {
+       /*
+        * Used for the 2nd Linux.
+        * TODO: M4 may use these pins.
+        */
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX     0x49
+                       MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX     0x49
+               >;
+       };
+};
+
+&{/busfreq} {
+       /* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */
+       status = "disabled";
+};
+
+&resmem {
+       jh_reserved: jh@fdc00000 {
+               no-map;
+               reg = <0 0xfdc00000 0x0 0x400000>;
+       };
+
+       inmate_reserved: inmate@c0000000 {
+               no-map;
+               reg = <0 0xc0000000 0x0 0x3dc00000>;
+       };
+
+       loader_reserved: loader@bff00000 {
+               no-map;
+               reg = <0 0xbff00000 0x0 0x00100000>;
+       };
+
+       ivshmem_reserved: ivshmem@bfe00000 {
+               no-map;
+               reg = <0 0xbfe00000 0x0 0x00100000>;
+       };
+
+       ivshmem2_reserved: ivshmem2@bfd00000 {
+               no-map;
+               reg = <0 0xbfd00000 0x0 0x00100000>;
+       };
+
+       pci_reserved: pci@bfc00000 {
+               no-map;
+               reg = <0 0xbfb00000 0x0 0x00200000>;
+       };
+};
+
+&uart1 {
+       /* uart2 is used by the 2nd OS, so configure pin and clk */
+       pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>;
+       assigned-clocks = <&clk IMX8MQ_CLK_UART1>,
+                       <&clk IMX8MQ_CLK_UART2>;
+       assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
+                       <&clk IMX8MQ_CLK_25M>;
+};
+
+&usdhc1 {
+       status = "disabled";
+};
+
+&usdhc2 {
+       /* sdhc1 is used by 2nd linux, configure the pin */
+       pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>;
+       pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>;
+};