There are several DPU units which have the same clock enable control bits
in their Dynamic registers, e.g., HScaler, VScaler, Rop, Fliter and Matrix,
etc. So, let's remove the prefix 'lb_' from the enumerator name of
lb_pixengcfg_clk_t so that it can be a little bit generic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
EXPORT_SYMBOL_GPL(layerblend_pixengcfg_dynamic_sec_sel);
void layerblend_pixengcfg_clken(struct dpu_layerblend *lb,
- lb_pixengcfg_clken_t clken)
+ pixengcfg_clken_t clken)
{
u32 val;
CLKEN__DISABLE = 0x0,
CLKEN__AUTOMATIC = 0x1,
CLKEN__FULL = 0x3,
-} lb_pixengcfg_clken_t;
+} pixengcfg_clken_t;
int dpu_map_irq(struct dpu_soc *dpu, int irq);
void layerblend_pixengcfg_dynamic_sec_sel(struct dpu_layerblend *lb,
lb_sec_sel_t sec);
void layerblend_pixengcfg_clken(struct dpu_layerblend *lb,
- lb_pixengcfg_clken_t clken);
+ pixengcfg_clken_t clken);
void layerblend_shden(struct dpu_layerblend *lb, bool enable);
void layerblend_shdtoksel(struct dpu_layerblend *lb, lb_shadow_sel_t sel);
void layerblend_shdldsel(struct dpu_layerblend *lb, lb_shadow_sel_t sel);