MLK-16918-8: arm64: dtsi: fsl-imx8qm: Update dtsi for nwl-mipi-dsi

Now, the NWL MIPI-DSI driver is implemented as a real bridge and uses
the "nwl,mipi-dsi" compatible.
This patch updates the mipi-dsi nodes to comply with the new design of
NWL and NWL_IMX drivers.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index c7e02a7..527413e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -1313,24 +1313,41 @@
                status = "disabled";
        };
 
-       mipi_dsi1: mipi_dsi@56228000 {
+       mipi_dsi_bridge1: mipi_dsi_bridge@56228000 {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "fsl,imx8qm-mipi-dsi";
+               compatible = "nwl,mipi-dsi";
                reg = <0x0 0x56228000 0x0 0x300>;
                interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-parent = <&irqsteer_dsi0>;
                clocks =
-                       <&clk IMX8QM_MIPI0_PXL_CLK>,
-                       <&clk IMX8QM_MIPI0_BYPASS_CLK>,
                        <&clk IMX8QM_CLK_DUMMY>,
                        <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>,
                        <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>;
-               clock-names = "pixel", "bypass", "phy_ref", "tx_esc", "rx_esc";
+               clock-names = "phy_ref", "tx_esc", "rx_esc";
                assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>,
                                  <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>;
                assigned-clock-rates = <18000000>, <72000000>;
                power-domains = <&pd_mipi0>;
+               phys = <&mipi_dsi_phy1>;
+               phy-names = "dphy";
+               status = "disabled";
+
+               port@0 {
+                       mipi_dsi_bridge1_in: endpoint {
+                               remote-endpoint = <&mipi_dsi1_out>;
+                       };
+               };
+       };
+
+       mipi_dsi1: mipi_dsi@56228000 {
+               compatible = "fsl,imx8qm-mipi-dsi";
+               clocks =
+                       <&clk IMX8QM_MIPI0_PXL_CLK>,
+                       <&clk IMX8QM_MIPI0_BYPASS_CLK>,
+                       <&clk IMX8QM_CLK_DUMMY>;
+               clock-names = "pixel", "bypass", "phy_ref";
+               power-domains = <&pd_mipi0>;
                csr = <&mipi_dsi_csr1>;
                phys = <&mipi_dsi_phy1>;
                phy-names = "dphy";
@@ -1341,6 +1358,12 @@
                                remote-endpoint = <&dpu1_disp0_mipi_dsi>;
                        };
                };
+
+               port@1 {
+                       mipi_dsi1_out: endpoint {
+                               remote-endpoint = <&mipi_dsi_bridge1_in>;
+                       };
+               };
        };
 
        lvds_region1: lvds_region@56240000 {
@@ -1516,24 +1539,41 @@
                status = "disabled";
        };
 
-       mipi_dsi2: mipi_dsi@57228000 {
+       mipi_dsi_bridge2: mipi_dsi_bridge@57228000 {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "fsl,imx8qm-mipi-dsi";
+               compatible = "nwl,mipi-dsi";
                reg = <0x0 0x57228000 0x0 0x300>;
                interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-parent = <&irqsteer_dsi1>;
                clocks =
-                       <&clk IMX8QM_MIPI1_PXL_CLK>,
-                       <&clk IMX8QM_MIPI1_BYPASS_CLK>,
                        <&clk IMX8QM_CLK_DUMMY>,
                        <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>,
                        <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>;
-               clock-names = "pixel", "bypass", "phy_ref", "tx_esc", "rx_esc";
+               clock-names = "phy_ref", "tx_esc", "rx_esc";
                assigned-clocks = <&clk IMX8QM_MIPI1_DSI_TX_ESC_DIV>,
                                  <&clk IMX8QM_MIPI1_DSI_RX_ESC_DIV>;
                assigned-clock-rates = <18000000>, <72000000>;
                power-domains = <&pd_mipi1>;
+               phys = <&mipi_dsi_phy2>;
+               phy-names = "dphy";
+               status = "disabled";
+
+               port@0 {
+                       mipi_dsi_bridge2_in: endpoint {
+                               remote-endpoint = <&mipi_dsi2_out>;
+                       };
+               };
+       };
+
+       mipi_dsi2: mipi_dsi@57228000 {
+               compatible = "fsl,imx8qm-mipi-dsi";
+               clocks =
+                       <&clk IMX8QM_MIPI1_PXL_CLK>,
+                       <&clk IMX8QM_MIPI1_BYPASS_CLK>,
+                       <&clk IMX8QM_CLK_DUMMY>;
+               clock-names = "pixel", "bypass", "phy_ref";
+               power-domains = <&pd_mipi1>;
                csr = <&mipi_dsi_csr2>;
                phys = <&mipi_dsi_phy2>;
                phy-names = "dphy";
@@ -1544,6 +1584,12 @@
                                remote-endpoint = <&dpu2_disp0_mipi_dsi>;
                        };
                };
+
+               port@1 {
+                       mipi_dsi2_out: endpoint {
+                               remote-endpoint = <&mipi_dsi_bridge2_in>;
+                       };
+               };
        };
 
        lvds_region2: lvds_region@57240000 {