MLK-14445-2 mx7ulp_evk: Add QSPI flash support

Porting the QSPI flash board support from v2016.03, and convert to use
DM QSPI driver.
Since we need to support QSPI at default in u-boot, change the default
DTS file to qspi enabled DTS.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 41895cd598be6c4a64fc4fec521120e4962abc28)
(cherry picked from commit b4698ce0e5b6952a88702075ce905a059da277d9)
(cherry picked from commit 2fa81543fa49924a92a470cce62fbca7544ecd56)
(cherry picked from commit e8795e4dc6eb5f3c9583e1d787368ff1e1ffb48f)
(cherry picked from commit 014ffa93579624d52571e0914af7f9166a73d5bb)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 39724b3..1e143a1 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -789,7 +789,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
-       imx7ulp-evk.dtb
+       imx7ulp-evk.dtb \
+       imx7ulp-evk-qspi.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += \
        fsl-imx8qm-apalis.dtb \

diff --git a/arch/arm/dts/imx7ulp-evk-qspi.dts b/arch/arm/dts/imx7ulp-evk-qspi.dts
new file mode 100644 (file)
index 0000000..982a172
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-evk-qspi.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7ulp-evk.dts"
+
+&qspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_qspi1_1>;
+       status = "okay";
+
+       flash0: mx25r6435f@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "macronix,mx25r6435f", "jedec,spi-nor";
+               spi-max-frequency = <29000000>;
+       };
+};
+
+&iomuxc {
+       status = "okay";
+};
+
+&iomuxc {
+       imx7ulp-evk {
+               pinctrl_qspi1_1: qspi1grp_1 {
+                       fsl,pins = <
+                               IMX7ULP_PAD_PTB7__QSPIA_SS1_B    0x43 /* SS1 */
+                               IMX7ULP_PAD_PTB8__QSPIA_SS0_B    0x43 /* SS0 */
+                               IMX7ULP_PAD_PTB15__QSPIA_SCLK    0x43 /* SCLK */
+                               IMX7ULP_PAD_PTB9__QSPIA_DQS      0x43 /* DQS */
+                               IMX7ULP_PAD_PTB16__QSPIA_DATA3   0x43 /* D3 */
+                               IMX7ULP_PAD_PTB17__QSPIA_DATA2   0x43 /* D2 */
+                               IMX7ULP_PAD_PTB18__QSPIA_DATA1   0x43 /* D1 */
+                               IMX7ULP_PAD_PTB19__QSPIA_DATA0   0x43 /* D0 */
+                       >;
+               };
+       };
+};
+

diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
index 01e3213..1e304a2 100644 (file)
--- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c
+++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
@@ -16,6 +16,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PUS_UP)
+#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE)
 
 int dram_init(void)
 {
@@ -35,6 +36,36 @@ static void setup_iomux_uart(void)
                                         ARRAY_SIZE(lpuart4_pads));
 }
 
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+static iomux_cfg_t const quadspi_pads[] = {
+       MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+       MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+       MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+       MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+       MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+       MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
+
+int board_qspi_init(void)
+{
+       u32 val;
+#ifndef CONFIG_DM_SPI
+       mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+#endif
+
+       /* enable clock */
+       val = readl(PCC1_RBASE + 0x94);
+
+       if (!(val & 0x20000000)) {
+               writel(0x03000003, (PCC1_RBASE + 0x94));
+               writel(0x43000003, (PCC1_RBASE + 0x94));
+       }
+       return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
@@ -47,6 +78,10 @@ int board_init(void)
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_FSL_QSPI
+       board_qspi_init();
+#endif
+
        return 0;
 }
 

diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index e918634..27864b4 100644 (file)
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_MX7ULP_EVK=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_BOARD_EARLY_INIT_F=y
@@ -43,3 +43,14 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0

diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index 8a80f89..5139825 100644 (file)
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -8,7 +8,8 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xC0000
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_MX7ULP_EVK=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
+CONFIG_USE_IMXIMG_PLUGIN=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
@@ -41,3 +42,14 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0