drm/i915/display/icl+: Do not program clockgating

Talked with HW team and this is a left over, driver should not
program clockgating, mg or dekel firmware is reponsible for any
clockgating programing.

Also removing the register and bits definition related to clockgating.

v2:
Added WARN_ON

v3:
Only calling icl_phy_set_clock_gating() on intel_ddi_pre_enable_hdmi
for GEN11

v4:
ICL should also not program clockgating (thanks Matt for catching
this)

BSpec issue: 20885
BSpec: 49292
BSpec: 21735
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200107170922.153612-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 07acd0d..2e4e178 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3167,57 +3167,6 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
        }
 }
 
-static void
-icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable)
-{
-       struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-       enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
-       u32 val, bits;
-       int ln;
-
-       if (tc_port == PORT_TC_NONE)
-               return;
-
-       bits = MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
-              MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
-              MG_DP_MODE_CFG_GAONPWR_GATING;
-
-       for (ln = 0; ln < 2; ln++) {
-               if (INTEL_GEN(dev_priv) >= 12) {
-                       I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
-                       val = I915_READ(DKL_DP_MODE(tc_port));
-               } else {
-                       val = I915_READ(MG_DP_MODE(ln, tc_port));
-               }
-
-               if (enable)
-                       val |= bits;
-               else
-                       val &= ~bits;
-
-               if (INTEL_GEN(dev_priv) >= 12)
-                       I915_WRITE(DKL_DP_MODE(tc_port), val);
-               else
-                       I915_WRITE(MG_DP_MODE(ln, tc_port), val);
-       }
-
-       if (INTEL_GEN(dev_priv) == 11) {
-               bits = MG_MISC_SUS0_CFG_TR2PWR_GATING |
-                      MG_MISC_SUS0_CFG_CL2PWR_GATING |
-                      MG_MISC_SUS0_CFG_GAONPWR_GATING |
-                      MG_MISC_SUS0_CFG_TRPWR_GATING |
-                      MG_MISC_SUS0_CFG_CL1PWR_GATING |
-                      MG_MISC_SUS0_CFG_DGPWR_GATING;
-
-               val = I915_READ(MG_MISC_SUS0(tc_port));
-               if (enable)
-                       val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3));
-               else
-                       val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK);
-               I915_WRITE(MG_MISC_SUS0(tc_port), val);
-       }
-}
-
 static void
 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
                       const struct intel_crtc_state *crtc_state)
@@ -3516,12 +3465,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
         * down this function.
         */
 
-       /*
-        * 7.d Type C with DP alternate or fixed/legacy/static connection -
-        * Disable PHY clock gating per Type-C DDI Buffer page
-        */
-       icl_phy_set_clock_gating(dig_port, false);
-
        /* 7.e Configure voltage swing and related IO settings */
        tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
                                encoder->type);
@@ -3573,15 +3516,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
        if (!is_trans_port_sync_mode(crtc_state))
                intel_dp_stop_link_train(intel_dp);
 
-       /*
-        * TODO: enable clock gating
-        *
-        * It is not written in DP enabling sequence but "PHY Clockgating
-        * programming" states that clock gating should be enabled after the
-        * link training but doing so causes all the following trainings to fail
-        * so not enabling it for now.
-        */
-
        /* 7.l Configure and enable FEC if needed */
        intel_ddi_enable_fec(encoder, crtc_state);
        intel_dsc_enable(encoder, crtc_state);
@@ -3617,7 +3551,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
                                        dig_port->ddi_io_power_domain);
 
        icl_program_mg_dp_mode(dig_port, crtc_state);
-       icl_phy_set_clock_gating(dig_port, false);
 
        if (INTEL_GEN(dev_priv) >= 11)
                icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
@@ -3651,8 +3584,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
 
        intel_ddi_enable_fec(encoder, crtc_state);
 
-       icl_phy_set_clock_gating(dig_port, true);
-
        if (!is_mst)
                intel_ddi_enable_pipe_clock(crtc_state);
 
@@ -3694,7 +3625,6 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
        intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
 
        icl_program_mg_dp_mode(dig_port, crtc_state);
-       icl_phy_set_clock_gating(dig_port, false);
 
        if (INTEL_GEN(dev_priv) >= 12)
                tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
@@ -3709,8 +3639,6 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
        else
                intel_prepare_hdmi_ddi_buffers(encoder, level);
 
-       icl_phy_set_clock_gating(dig_port, true);
-
        if (IS_GEN9_BC(dev_priv))
                skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d90d7bf..6cc55c1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2244,26 +2244,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
                                    MG_DP_MODE_LN1_ACU_PORT1)
 #define   MG_DP_MODE_CFG_DP_X2_MODE                    (1 << 7)
 #define   MG_DP_MODE_CFG_DP_X1_MODE                    (1 << 6)
-#define   MG_DP_MODE_CFG_TR2PWR_GATING                 (1 << 5)
-#define   MG_DP_MODE_CFG_TRPWR_GATING                  (1 << 4)
-#define   MG_DP_MODE_CFG_CLNPWR_GATING                 (1 << 3)
-#define   MG_DP_MODE_CFG_DIGPWR_GATING                 (1 << 2)
-#define   MG_DP_MODE_CFG_GAONPWR_GATING                        (1 << 1)
-
-#define MG_MISC_SUS0_PORT1                             0x168814
-#define MG_MISC_SUS0_PORT2                             0x169814
-#define MG_MISC_SUS0_PORT3                             0x16A814
-#define MG_MISC_SUS0_PORT4                             0x16B814
-#define MG_MISC_SUS0(tc_port) \
-       _MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))
-#define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK     (3 << 14)
-#define   MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x)       ((x) << 14)
-#define   MG_MISC_SUS0_CFG_TR2PWR_GATING               (1 << 12)
-#define   MG_MISC_SUS0_CFG_CL2PWR_GATING               (1 << 11)
-#define   MG_MISC_SUS0_CFG_GAONPWR_GATING              (1 << 10)
-#define   MG_MISC_SUS0_CFG_TRPWR_GATING                        (1 << 7)
-#define   MG_MISC_SUS0_CFG_CL1PWR_GATING               (1 << 6)
-#define   MG_MISC_SUS0_CFG_DGPWR_GATING                        (1 << 5)
 
 /* The spec defines this only for BXT PHY0, but lets assume that this
  * would exist for PHY1 too if it had a second channel.