The HDMI digital PLL, bus clock and core clock need to change to improve the
firmware loading time. The clock are now set to 800 MHz for DPLL, 200 MHz for
HDMI core, and 100 MHz for HDMI bus.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
(cherry picked from commit
1d368140f32cce8fc35962b18da6332d383bb094)
static void display_set_clocks(void)
{
- const sc_pm_clock_rate_t pll = 657000000;
- const sc_pm_clock_rate_t hdmi_core_clock = pll / 5; /* 135.000 Mhz */
- const sc_pm_clock_rate_t hdmi_bus_clock = pll / 8; /* 83.375 Mhz */
+ const sc_pm_clock_rate_t pll = 800000000;
+ const sc_pm_clock_rate_t hdmi_core_clock = pll / 4; /* 200 Mhz */
+ const sc_pm_clock_rate_t hdmi_bus_clock = pll / 8; /* 100 Mhz */
SC_PM_SET_RESOURCE_POWER_MODE(-1,
SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF);