MLK-14326-13 mx6ulevk: Add DTS files

Update i.MX6ul dtsi file and add mx6ul 14x14 and 9x9 evk DTS file
to latest in kernel.
To support DM QSPI driver, modify the DTS files with adding a spi0
alias for qspi node and changing the the n25q256a flash node's compatible
to "spi-flash"

Signed-off-by: Ye Li <ye.li@nxp.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1cf7619..f1fd1b8 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -309,9 +309,13 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
 
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+dtb-$(CONFIG_MX6) += imx6ul-14x14-evk.dtb \
+       imx6ul-14x14-evk-emmc.dtb \
+       imx6ul-14x14-evk-gpmi-weim.dtb \
+       imx6ull-14x14-evk.dtb \
        imx6ull-14x14-evk-emmc.dtb \
        imx6ull-14x14-evk-gpmi-weim.dtb \
+       imx6ul-9x9-evk.dtb \
        imx6ull-9x9-evk.dtb \
        imx6sll-evk.dtb \
        imx6dl-icore.dtb \

diff --git a/arch/arm/dts/imx6ul-14x14-evk-emmc.dts b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts
new file mode 100644 (file)
index 0000000..b56d34d
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts
@@ -0,0 +1,20 @@
+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-14x14-evk.dts"
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+       pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};

diff --git a/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts
new file mode 100644 (file)
index 0000000..7cff087
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-14x14-evk.dts"
+
+&gpmi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+       status = "okay";
+       nand-on-flash-bbt;
+};
+
+&iomuxc {
+       imx6ul-evk-gpmi-rework {
+               pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+                               MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+                               MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+                               MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+                               MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+                               MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+                               MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+                               MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+                               MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+                               MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+                               MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+                               MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+                               MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+                               MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+                               MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+                               MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+                       >;
+               };
+       };
+};
+
+&qspi {
+       status = "disabled";
+};
+
+&usdhc2 {
+       status = "disabled";
+};

diff --git a/arch/arm/dts/imx6ul-14x14-evk.dts b/arch/arm/dts/imx6ul-14x14-evk.dts
new file mode 100644 (file)
index 0000000..f2b3ec3
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-evk.dts
@@ -0,0 +1,753 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ul.dtsi"
+
+/ {
+       model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
+       compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       memory {
+               reg = <0x80000000 0x20000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x14000000>;
+                       linux,cma-default;
+               };
+       };
+
+       backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm1 0 5000000>;
+               brightness-levels = <0 4 8 16 32 64 128 255>;
+               default-brightness-level = <6>;
+               status = "okay";
+       };
+
+       pxp_v4l2 {
+               compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+               status = "okay";
+       };
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               reg_can_3v3: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "can-3v3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
+               };
+
+               reg_sd1_vmmc: regulator@1 {
+                       compatible = "regulator-fixed";
+                       regulator-name = "VSD_3V3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
+               reg_gpio_dvfs: regulator-gpio {
+                       compatible = "regulator-gpio";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_dvfs>;
+                       regulator-min-microvolt = <1300000>;
+                       regulator-max-microvolt = <1400000>;
+                       regulator-name = "gpio_dvfs";
+                       regulator-type = "voltage";
+                       gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+                       states = <1300000 0x1 1400000 0x0>;
+               };
+       };
+
+       sound: sound {
+               compatible = "fsl,imx6ul-evk-wm8960",
+                          "fsl,imx-audio-wm8960";
+               model = "wm8960-audio";
+               cpu-dai = <&sai2>;
+               audio-codec = <&codec>;
+               asrc-controller = <&asrc>;
+               codec-master;
+               gpr = <&gpr 4 0x100000 0x100000>;
+               /*
+                 * hp-det = <hp-det-pin hp-det-polarity>;
+                * hp-det-pin: JD1 JD2  or JD3
+                * hp-det-polarity = 0: hp detect high for headphone
+                * hp-det-polarity = 1: hp detect high for speaker
+                */
+               hp-det = <3 0>;
+               hp-det-gpios = <&gpio5 4 0>;
+               mic-det-gpios = <&gpio5 4 0>;
+               audio-routing =
+                       "Headphone Jack", "HP_L",
+                       "Headphone Jack", "HP_R",
+                       "Ext Spk", "SPK_LP",
+                       "Ext Spk", "SPK_LN",
+                       "Ext Spk", "SPK_RP",
+                       "Ext Spk", "SPK_RN",
+                       "LINPUT2", "Mic Jack",
+                       "LINPUT3", "Mic Jack",
+                       "RINPUT1", "Main MIC",
+                       "RINPUT2", "Main MIC",
+                       "Mic Jack", "MICB",
+                       "Main MIC", "MICB",
+                       "CPU-Playback", "ASRC-Playback",
+                       "Playback", "CPU-Playback",
+                       "ASRC-Capture", "CPU-Capture",
+                       "CPU-Capture", "Capture";
+       };
+
+       spi4 {
+               compatible = "spi-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_spi4>;
+               pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+               status = "okay";
+               gpio-sck = <&gpio5 11 0>;
+               gpio-mosi = <&gpio5 10 0>;
+               cs-gpios = <&gpio5 7 0>;
+               num-chipselects = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               gpio_spi: gpio_spi@0 {
+                       compatible = "fairchild,74hc595";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0>;
+                       registers-number = <1>;
+                       registers-default = /bits/ 8 <0x57>;
+                       spi-max-frequency = <100000>;
+               };
+       };
+};
+
+&cpu0 {
+       arm-supply = <&reg_arm>;
+       soc-supply = <&reg_soc>;
+       dc-supply = <&reg_gpio_dvfs>;
+};
+
+&clks {
+       assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+       assigned-clock-rates = <786432000>;
+};
+
+&csi {
+       status = "disabled";
+
+       port {
+               csi1_ep: endpoint {
+                       remote-endpoint = <&ov5640_ep>;
+               };
+       };
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy0>;
+       status = "okay";
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy1>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@2 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <2>;
+               };
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       xceiver-supply = <&reg_can_3v3>;
+       status = "okay";
+};
+
+&flexcan2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       xceiver-supply = <&reg_can_3v3>;
+       status = "okay";
+};
+
+&gpc {
+       fsl,cpu_pupscr_sw2iso = <0x1>;
+       fsl,cpu_pupscr_sw = <0x0>;
+       fsl,cpu_pdnscr_iso2sw = <0x1>;
+       fsl,cpu_pdnscr_iso = <0x1>;
+       fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&i2c1 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       mag3110@0e {
+               compatible = "fsl,mag3110";
+               reg = <0x0e>;
+               position = <2>;
+       };
+
+       fxls8471@1e {
+               compatible = "fsl,fxls8471";
+               reg = <0x1e>;
+               position = <0>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <0 8>;
+       };
+};
+
+&i2c2 {
+       clock_frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       codec: wm8960@1a {
+               compatible = "wlf,wm8960";
+               reg = <0x1a>;
+               clocks = <&clks IMX6UL_CLK_SAI2>;
+               clock-names = "mclk";
+               wlf,shared-lrclk;
+       };
+
+       ov5640: ov5640@3c {
+               compatible = "ovti,ov5640";
+               reg = <0x3c>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_csi1>;
+               clocks = <&clks IMX6UL_CLK_CSI>;
+               clock-names = "csi_mclk";
+               pwn-gpios = <&gpio_spi 6 1>;
+               rst-gpios = <&gpio_spi 5 0>;
+               csi_id = <0>;
+               mclk = <24000000>;
+               mclk_source = <0>;
+               status = "disabled";
+               port {
+                       ov5640_ep: endpoint {
+                               remote-endpoint = <&csi1_ep>;
+                       };
+               };
+       };
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog_1>;
+       imx6ul-evk {
+               pinctrl_hog_1: hoggrp-1 {
+                       fsl,pins = <
+                               MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
+                               MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+                               MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+                               MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+                       >;
+               };
+
+               pinctrl_csi1: csi1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
+                               MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
+                               MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
+                               MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
+                               MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
+                               MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
+                               MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
+                               MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
+                               MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
+                               MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
+                               MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
+                               MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
+                       >;
+               };
+
+               pinctrl_dvfs: dvfsgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
+                       >;
+               };
+
+               pinctrl_enet1: enet1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                               MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+                               MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                               MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                               MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                               MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                               MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                               MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                       >;
+               };
+
+               pinctrl_enet2: enet2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                               MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+                               MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                               MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                               MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                               MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                               MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                               MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                               MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                               MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                       >;
+               };
+
+               pinctrl_flexcan1: flexcan1grp{
+                       fsl,pins = <
+                               MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
+                               MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
+                       >;
+               };
+
+               pinctrl_flexcan2: flexcan2grp{
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
+                               MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
+                       >;
+               };
+
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                               MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+                       >;
+               };
+
+               pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+                               MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+                       >;
+               };
+
+               pinctrl_lcdif_dat: lcdifdatgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+                               MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+                               MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+                               MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+                               MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+                               MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+                               MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+                               MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+                               MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+                               MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+                               MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+                               MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+                               MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+                               MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+                               MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+                               MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+                               MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+                               MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+                               MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+                               MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+                               MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+                               MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+                               MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+                               MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+                       >;
+               };
+
+               pinctrl_lcdif_ctrl: lcdifctrlgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
+                               MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+                               MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+                               MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+                               /* used for lcd reset */
+                               MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+                       >;
+               };
+
+               pinctrl_pf1550: pf1550 {
+                       fsl,pins = <
+                                MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x80000000
+                       >;
+               };
+
+               pinctrl_pwm1: pwm1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
+                       >;
+               };
+
+               pinctrl_qspi: qspigrp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+                               MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+                               MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+                               MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+                               MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+                               MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+                       >;
+               };
+
+               pinctrl_sai2: sai2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                               MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                               MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
+                               MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
+                               MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
+                               MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
+                       >;
+               };
+
+               pinctrl_sim2_1: sim2grp-1 {
+                       fsl,pins = <
+                               MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
+                               MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x11
+                               MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb810
+                               MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb810
+                               MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb811
+                               MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
+                       >;
+               };
+
+               pinctrl_spi4: spi4grp {
+                       fsl,pins = <
+                               MX6UL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
+                               MX6UL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
+                               MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
+                               MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
+                       >;
+               };
+
+               pinctrl_tsc: tscgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
+                               MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0xb0
+                               MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
+                               MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+                               MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+                       >;
+               };
+
+               pinctrl_uart2: uart2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+                               MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+                               MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
+                               MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
+                       >;
+               };
+
+               pinctrl_uart2dte: uart2dtegrp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
+                               MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
+                               MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS  0x1b0b1
+                               MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS  0x1b0b1
+                       >;
+               };
+
+               pinctrl_usdhc1: usdhc1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+                               MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
+                               MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+                               MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+                               MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+                               MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+                       >;
+               };
+
+               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+                               MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+                               MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+                               MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+                               MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+                               MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+                       >;
+               };
+
+               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+                               MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+                               MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+                               MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+                               MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+                               MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+                       >;
+               };
+
+               pinctrl_usdhc2: usdhc2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+                       >;
+               };
+
+               pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+                               MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+                               MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+                               MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+                               MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+                       >;
+               };
+
+               pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+                               MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+                               MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+                               MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+                               MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+                       >;
+               };
+
+               pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+                               MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+                               MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+                               MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+                               MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+                       >;
+               };
+               pinctrl_wdog: wdoggrp {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
+                       >;
+               };
+       };
+};
+
+&lcdif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lcdif_dat
+                    &pinctrl_lcdif_ctrl>;
+       display = <&display0>;
+       status = "okay";
+
+       display0: display {
+               bits-per-pixel = <16>;
+               bus-width = <24>;
+
+               display-timings {
+                       native-mode = <&timing0>;
+                       timing0: timing0 {
+                       clock-frequency = <9200000>;
+                       hactive = <480>;
+                       vactive = <272>;
+                       hfront-porch = <8>;
+                       hback-porch = <4>;
+                       hsync-len = <41>;
+                       vback-porch = <2>;
+                       vfront-porch = <4>;
+                       vsync-len = <10>;
+
+                       hsync-active = <0>;
+                       vsync-active = <0>;
+                       de-active = <1>;
+                       pixelclk-active = <0>;
+                       };
+               };
+       };
+};
+
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm1>;
+       status = "okay";
+};
+
+&pxp {
+       status = "okay";
+};
+
+&qspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_qspi>;
+       status = "okay";
+       ddrsmp=<0>;
+
+       flash0: n25q256a@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <29000000>;
+               spi-nor,ddr-quad-read-dummy = <6>;
+               reg = <0>;
+       };
+};
+
+&sai2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai2>;
+
+       assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+                         <&clks IMX6UL_CLK_SAI2>;
+       assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+       assigned-clock-rates = <0>, <12288000>;
+
+       status = "okay";
+};
+
+&sim2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sim2_1>;
+       assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
+       assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
+       assigned-clock-rates = <240000000>;
+       /* GPIO_ACTIVE_HIGH/LOW:sim card voltage control
+        * NCN8025:Vcc = ACTIVE_HIGH?5V:3V
+        * TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V
+        */
+       pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+       port = <1>;
+       sven_low_active;
+       status = "okay";
+};
+
+&tsc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_tsc>;
+       xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+       measure-delay-time = <0xffff>;
+       pre-charge-time = <0xfff>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       fsl,uart-has-rtscts;
+       /* for DTE mode, add below change */
+       /* fsl,dte-mode; */
+       /* pinctrl-0 = <&pinctrl_uart2dte>; */
+       status = "okay";
+};
+
+&usbotg1 {
+       dr_mode = "otg";
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       status = "okay";
+};
+
+&usbotg2 {
+       dr_mode = "host";
+       disable-over-current;
+       status = "okay";
+};
+
+&usbphy1 {
+       tx-d-cal = <0x5>;
+};
+
+&usbphy2 {
+       tx-d-cal = <0x5>;
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+       keep-power-in-suspend;
+       enable-sdio-wakeup;
+       vmmc-supply = <&reg_sd1_vmmc>;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       non-removable;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,wdog_b;
+};

diff --git a/arch/arm/dts/imx6ul-9x9-evk.dts b/arch/arm/dts/imx6ul-9x9-evk.dts
new file mode 100644 (file)
index 0000000..04a562b
--- /dev/null
+++ b/arch/arm/dts/imx6ul-9x9-evk.dts
@@ -0,0 +1,805 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ul.dtsi"
+
+/ {
+       model = "Freescale i.MX6 UltraLite 9x9 EVK Board";
+       compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
+
+       backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm1 0 5000000>;
+               brightness-levels = <0 4 8 16 32 64 128 255>;
+               default-brightness-level = <6>;
+               status = "okay";
+       };
+
+       chosen {
+               stdout-path = &uart1;
+       };
+
+       memory {
+               reg = <0x80000000 0x10000000>;
+       };
+
+       reserved-memory {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               linux,cma {
+                       compatible = "shared-dma-pool";
+                       reusable;
+                       size = <0x6000000>;
+                       linux,cma-default;
+               };
+       };
+
+       pxp_v4l2 {
+               compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+               status = "okay";
+       };
+
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               reg_can_3v3: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "can-3v3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
+               };
+
+               reg_gpio_dvfs: regulator-gpio {
+                       compatible = "regulator-gpio";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_dvfs>;
+                       regulator-min-microvolt = <1300000>;
+                       regulator-max-microvolt = <1400000>;
+                       regulator-name = "gpio_dvfs";
+                       regulator-type = "voltage";
+                       gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+                       states = <1300000 0x1 1400000 0x0>;
+               };
+
+               reg_sd1_vmmc: regulator@1 {
+                       compatible = "regulator-fixed";
+                       regulator-name = "VSD_3V3";
+                       regulator-min-microvolt = <3300000>;
+                       regulator-max-microvolt = <3300000>;
+                       gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+       };
+
+       sound {
+               compatible = "fsl,imx6ul-evk-wm8960",
+                          "fsl,imx-audio-wm8960";
+               model = "wm8960-audio";
+               cpu-dai = <&sai2>;
+               audio-codec = <&codec>;
+               asrc-controller = <&asrc>;
+               codec-master;
+               gpr = <&gpr 4 0x100000 0x100000>;
+               /*
+                 * hp-det = <hp-det-pin hp-det-polarity>;
+                * hp-det-pin: JD1 JD2  or JD3
+                * hp-det-polarity = 0: hp detect high for headphone
+                * hp-det-polarity = 1: hp detect high for speaker
+                */
+               hp-det = <3 0>;
+               hp-det-gpios = <&gpio5 4 0>;
+               mic-det-gpios = <&gpio5 4 0>;
+               audio-routing =
+                       "Headphone Jack", "HP_L",
+                       "Headphone Jack", "HP_R",
+                       "Ext Spk", "SPK_LP",
+                       "Ext Spk", "SPK_LN",
+                       "Ext Spk", "SPK_RP",
+                       "Ext Spk", "SPK_RN",
+                       "LINPUT2", "Mic Jack",
+                       "LINPUT3", "Mic Jack",
+                       "RINPUT1", "Main MIC",
+                       "RINPUT2", "Main MIC",
+                       "Mic Jack", "MICB",
+                       "Main MIC", "MICB",
+                       "CPU-Playback", "ASRC-Playback",
+                       "Playback", "CPU-Playback",
+                       "ASRC-Capture", "CPU-Capture",
+                       "CPU-Capture", "Capture";
+       };
+
+       spi4 {
+               compatible = "spi-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_spi4>;
+               pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+               status = "okay";
+               gpio-sck = <&gpio5 11 0>;
+               gpio-mosi = <&gpio5 10 0>;
+               cs-gpios = <&gpio5 7 0>;
+               num-chipselects = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               gpio_spi: gpio_spi@0 {
+                       compatible = "fairchild,74hc595";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       reg = <0>;
+                       registers-number = <1>;
+                       registers-default = /bits/ 8 <0x57>;
+                       spi-max-frequency = <100000>;
+               };
+       };
+};
+
+&clks {
+       assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+       assigned-clock-rates = <786432000>;
+};
+
+&cpu0 {
+       /*
+        * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
+        * to align with other platform and use the same cpufreq
+        * driver, still use the seperated OPP define for arm
+        * and soc.
+        */
+       operating-points = <
+               /* kHz  uV */
+               528000  1175000
+               396000  1175000
+               198000  1175000
+       >;
+       fsl,soc-operating-points = <
+               /* KHz  uV */
+               528000  1175000
+               396000  1175000
+               198000  1175000
+       >;
+       arm-supply = <&sw1c_reg>;
+       soc-supply = <&sw1c_reg>;
+       fsl,arm-soc-shared = <1>;
+};
+
+&csi {
+       status = "disabled";
+
+       port {
+               csi1_ep: endpoint {
+                       remote-endpoint = <&ov5640_ep>;
+               };
+       };
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy0>;
+       status = "okay";
+};
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2>;
+       phy-mode = "rmii";
+       phy-handle = <&ethphy1>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@2 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <2>;
+               };
+
+               ethphy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <1>;
+               };
+       };
+};
+
+&flexcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan1>;
+       xceiver-supply = <&reg_can_3v3>;
+       status = "okay";
+};
+
+&flexcan2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       xceiver-supply = <&reg_can_3v3>;
+       status = "okay";
+};
+
+&gpc {
+       fsl,cpu_pupscr_sw2iso = <0x1>;
+       fsl,cpu_pupscr_sw = <0x0>;
+       fsl,cpu_pdnscr_iso2sw = <0x1>;
+       fsl,cpu_pdnscr_iso = <0x1>;
+       fsl,wdog-reset = <1>; /* watchdog select of reset source */
+       fsl,ldo-bypass = <1>;
+};
+
+&i2c1 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       pmic: pfuze3000@08 {
+               compatible = "fsl,pfuze3000";
+               reg = <0x08>;
+
+               regulators {
+                       sw1a_reg: sw1a {
+                                       regulator-min-microvolt = <700000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-boot-on;
+                                       regulator-always-on;
+                                       regulator-ramp-delay = <6250>;
+                       };
+
+                       /* use sw1c_reg to align with pfuze100/pfuze200 */
+                       sw1c_reg: sw1b {
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1475000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <6250>;
+                       };
+
+                       sw2_reg: sw2 {
+                               regulator-min-microvolt = <2500000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       sw3a_reg: sw3 {
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1650000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       swbst_reg: swbst {
+                               regulator-min-microvolt = <5000000>;
+                               regulator-max-microvolt = <5150000>;
+                       };
+
+                       snvs_reg: vsnvs {
+                               regulator-min-microvolt = <1000000>;
+                               regulator-max-microvolt = <3000000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vref_reg: vrefddr {
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       vgen1_reg: vldo1 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen2_reg: vldo2 {
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1550000>;
+                               regulator-always-on;
+                       };
+
+                       vgen3_reg: vccsd {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen4_reg: v33 {
+                               regulator-min-microvolt = <2850000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen5_reg: vldo3 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+
+                       vgen6_reg: vldo4 {
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-always-on;
+                       };
+               };
+       };
+
+       mag3110@0e {
+               compatible = "fsl,mag3110";
+               reg = <0x0e>;
+               position = <2>;
+       };
+
+       fxls8471@1e {
+               compatible = "fsl,fxls8471";
+               reg = <0x1e>;
+               position = <0>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <0 8>;
+       };
+};
+
+&i2c2 {
+       clock_frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       codec: wm8960@1a {
+               compatible = "wlf,wm8960";
+               reg = <0x1a>;
+               clocks = <&clks IMX6UL_CLK_SAI2>;
+               clock-names = "mclk";
+               wlf,shared-lrclk;
+       };
+
+       ov5640: ov5640@3c {
+               compatible = "ovti,ov5640";
+               reg = <0x3c>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_csi1>;
+               clocks = <&clks IMX6UL_CLK_CSI>;
+               clock-names = "csi_mclk";
+               pwn-gpios = <&gpio_spi 6 1>;
+               rst-gpios = <&gpio_spi 5 0>;
+               csi_id = <0>;
+               mclk = <24000000>;
+               mclk_source = <0>;
+               status = "disabled";
+               port {
+                       ov5640_ep: endpoint {
+                               remote-endpoint = <&csi1_ep>;
+                       };
+               };
+       };
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog_1>;
+       imx6ul-evk {
+               pinctrl_csi1: csi1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
+                               MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
+                               MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
+                               MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
+                               MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
+                               MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
+                               MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
+                               MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
+                               MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
+                               MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
+                               MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
+                               MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
+                       >;
+               };
+
+               pinctrl_dvfs: dvfsgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
+                       >;
+               };
+
+               pinctrl_enet1: enet1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                               MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+                               MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                               MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                               MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                               MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                               MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                               MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                       >;
+               };
+
+               pinctrl_enet2: enet2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                               MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+                               MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                               MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                               MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                               MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                               MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                               MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                               MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                               MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                               MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+                       >;
+               };
+
+               pinctrl_flexcan1: flexcan1grp{
+                       fsl,pins = <
+                               MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
+                               MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
+                       >;
+               };
+
+               pinctrl_flexcan2: flexcan2grp{
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
+                               MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
+                       >;
+               };
+
+               pinctrl_hog_1: hoggrp-1 {
+                       fsl,pins = <
+                               MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
+                               MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+                               MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+                       >;
+               };
+
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                               MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+                       >;
+               };
+
+               pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+                               MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+                       >;
+               };
+
+               pinctrl_lcdif_ctrl: lcdifctrlgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
+                               MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+                               MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+                               MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+                               /* used for lcd reset */
+                               MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+                       >;
+               };
+
+               pinctrl_lcdif_dat: lcdifdatgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+                               MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+                               MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+                               MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+                               MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+                               MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+                               MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+                               MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+                               MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+                               MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+                               MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+                               MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+                               MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+                               MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+                               MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+                               MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+                               MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+                               MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+                               MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+                               MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+                               MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+                               MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+                               MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+                               MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+                       >;
+               };
+
+               pinctrl_pwm1: pwm1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
+                       >;
+               };
+
+               pinctrl_qspi: qspigrp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+                               MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+                               MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+                               MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+                               MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+                               MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+                       >;
+               };
+
+               pinctrl_sai2: sai2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                               MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                               MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
+                               MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
+                               MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
+                               MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
+                       >;
+               };
+
+               pinctrl_sim2_1: sim2grp-1 {
+                       fsl,pins = <
+                               MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
+                               MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
+                               MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
+                               MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
+                               MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
+                               MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
+                       >;
+               };
+
+               pinctrl_spi4: spi4grp {
+                       fsl,pins = <
+                               MX6UL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
+                               MX6UL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
+                               MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
+                               MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
+                       >;
+               };
+
+               pinctrl_tsc: tscgrp {
+                       fsl,pins = <
+                               MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
+                               MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0xb0
+                               MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
+                               MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+                               MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+                       >;
+               };
+
+               pinctrl_uart2: uart2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+                               MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+                               MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
+                               MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
+                       >;
+               };
+
+               pinctrl_uart2dte: uart2dtegrp {
+                       fsl,pins = <
+                               MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
+                               MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
+                               MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS  0x1b0b1
+                               MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS  0x1b0b1
+                       >;
+               };
+
+               pinctrl_usdhc1: usdhc1grp {
+                       fsl,pins = <
+                               MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+                               MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
+                               MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+                               MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+                               MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+                               MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+                       >;
+               };
+
+               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+                               MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+                               MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+                               MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+                               MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+                               MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+                       >;
+               };
+
+               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                       fsl,pins = <
+                               MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+                               MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+                               MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+                               MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+                               MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+                               MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+                       >;
+               };
+
+               pinctrl_usdhc2: usdhc2grp {
+                       fsl,pins = <
+                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
+                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+                       >;
+               };
+
+               pinctrl_wdog: wdoggrp {
+                       fsl,pins = <
+                               MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
+                       >;
+               };
+       };
+};
+
+&lcdif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lcdif_dat
+                    &pinctrl_lcdif_ctrl>;
+       display = <&display0>;
+       status = "okay";
+
+       display0: display {
+               bits-per-pixel = <16>;
+               bus-width = <24>;
+
+               display-timings {
+                       native-mode = <&timing0>;
+                       timing0: timing0 {
+                       clock-frequency = <9200000>;
+                       hactive = <480>;
+                       vactive = <272>;
+                       hfront-porch = <8>;
+                       hback-porch = <4>;
+                       hsync-len = <41>;
+                       vback-porch = <2>;
+                       vfront-porch = <4>;
+                       vsync-len = <10>;
+
+                       hsync-active = <0>;
+                       vsync-active = <0>;
+                       de-active = <1>;
+                       pixelclk-active = <0>;
+                       };
+               };
+       };
+};
+
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm1>;
+       status = "okay";
+};
+
+&pxp {
+       status = "okay";
+};
+
+&qspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_qspi>;
+       status = "okay";
+       ddrsmp=<0>;
+
+       flash0: n25q256a@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <29000000>;
+               spi-nor,ddr-quad-read-dummy = <6>;
+               reg = <0>;
+       };
+};
+
+&sai2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai2>;
+
+       assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+                         <&clks IMX6UL_CLK_SAI2>;
+       assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+       assigned-clock-rates = <0>, <12288000>;
+
+       status = "okay";
+};
+
+&sim2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sim2_1>;
+       assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
+       assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
+       assigned-clock-rates = <240000000>;
+       pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
+       port = <1>;
+       sven_low_active;
+       status = "okay";
+};
+
+&tsc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_tsc>;
+       xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+       measure_delay_time = <0xffff>;
+       pre_charge_time = <0xfff>;
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       status = "okay";
+};
+
+&uart2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       fsl,uart-has-rtscts;
+       /* for DTE mode, add below change */
+       /* fsl,dte-mode; */
+       /* pinctrl-0 = <&pinctrl_uart2dte>; */
+       status = "okay";
+};
+
+&usbotg1 {
+       dr_mode = "otg";
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       status = "okay";
+};
+
+&usbotg2 {
+       dr_mode = "host";
+       disable-over-current;
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+       keep-power-in-suspend;
+       enable-sdio-wakeup;
+       vmmc-supply = <&reg_sd1_vmmc>;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc2>;
+       no-1-8-v;
+       non-removable;
+       keep-power-in-suspend;
+       enable-sdio-wakeup;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,wdog_b;
+};

diff --git a/arch/arm/dts/imx6ul-pinfunc.h b/arch/arm/dts/imx6ul-pinfunc.h
index 0034eeb..1d43f51 100644 (file)
--- a/arch/arm/dts/imx6ul-pinfunc.h
+++ b/arch/arm/dts/imx6ul-pinfunc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,925 +14,948 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
-#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10               0x0014 0x02a0 0x0000 5 0
-#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11               0x0018 0x02a4 0x0000 5 0
-
-#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00             0x001c 0x02a8 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01             0x0020 0x02ac 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02             0x0024 0x02b0 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03             0x0028 0x02b4 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04             0x002c 0x02b8 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05             0x0030 0x02bc 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06             0x0034 0x02c0 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07             0x0038 0x02c4 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08             0x003c 0x02c8 0x0000 5 0
-#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09             0x0040 0x02cc 0x0000 5 0
-
-#define MX6UL_PAD_JTAG_MOD__SJC_MOD                    0x0044 0x02d0 0x0000 0 0
-#define MX6UL_PAD_JTAG_MOD__GPT2_CLK                   0x0044 0x02d0 0x05a0 1 0
-#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT                  0x0044 0x02d0 0x0000 2 0
-#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M          0x0044 0x02d0 0x0000 3 0
-#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY               0x0044 0x02d0 0x04c0 4 0
-#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10                 0x0044 0x02d0 0x0000 5 0
-#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00           0x0044 0x02d0 0x0000 6 0
-#define MX6UL_PAD_JTAG_TMS__SJC_TMS                    0x0048 0x02d4 0x0000 0 0
-#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1              0x0048 0x02d4 0x0598 1 0
-#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK                  0x0048 0x02d4 0x0000 2 0
-#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1                  0x0048 0x02d4 0x0000 3 0
-#define MX6UL_PAD_JTAG_TMS__CCM_WAIT                   0x0048 0x02d4 0x0000 4 0
-#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11                 0x0048 0x02d4 0x0000 5 0
-#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01           0x0048 0x02d4 0x0000 6 0
-#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT                  0x0048 0x02d4 0x0000 8 0
-#define MX6UL_PAD_JTAG_TDO__SJC_TDO                    0x004c 0x02d8 0x0000 0 0
-#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2              0x004c 0x02d8 0x059c 1 0
-#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC               0x004c 0x02d8 0x05fc 2 0
-#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2                  0x004c 0x02d8 0x0000 3 0
-#define MX6UL_PAD_JTAG_TDO__CCM_STOP                   0x004c 0x02d8 0x0000 4 0
-#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12                 0x004c 0x02d8 0x0000 5 0
-#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT                  0x004c 0x02d8 0x0000 6 0
-#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT                  0x004c 0x02d8 0x0000 8 0
-#define MX6UL_PAD_JTAG_TDI__SJC_TDI                    0x0050 0x02dc 0x0000 0 0
-#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1              0x0050 0x02dc 0x0000 1 0
-#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK               0x0050 0x02dc 0x05f8 2 0
-#define MX6UL_PAD_JTAG_TDI__PWM6_OUT                   0x0050 0x02dc 0x0000 4 0
-#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13                 0x0050 0x02dc 0x0000 5 0
-#define MX6UL_PAD_JTAG_TDI__MQS_LEFT                   0x0050 0x02dc 0x0000 6 0
-#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL            0x0050 0x02dc 0x0000 8 0
-#define MX6UL_PAD_JTAG_TCK__SJC_TCK                    0x0054 0x02e0 0x0000 0 0
-#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2              0x0054 0x02e0 0x0000 1 0
-#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA               0x0054 0x02e0 0x05f4 2 0
-#define MX6UL_PAD_JTAG_TCK__PWM7_OUT                   0x0054 0x02e0 0x0000 4 0
-#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14                 0x0054 0x02e0 0x0000 5 0
-#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL            0x0054 0x02e0 0x0000 8 0
-#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB               0x0058 0x02e4 0x0000 0 0
-#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3           0x0058 0x02e4 0x0000 1 0
-#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA            0x0058 0x02e4 0x0000 2 0
-#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT                        0x0058 0x02e4 0x0000 4 0
-#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15              0x0058 0x02e4 0x0000 5 0
-#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS                0x0058 0x02e4 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL                 0x005c 0x02e8 0x05ac 0 1
-#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1            0x005c 0x02e8 0x058c 1 0
-#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID           0x005c 0x02e8 0x04b8 2 0
-#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1           0x005c 0x02e8 0x0574 3 0
-#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT                        0x005c 0x02e8 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00               0x005c 0x02e8 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN     0x005c 0x02e8 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET         0x005c 0x02e8 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B             0x005c 0x02e8 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA                 0x0060 0x02ec 0x05b0 0 1
-#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1            0x0060 0x02ec 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC              0x0060 0x02ec 0x0664 2 0
-#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2           0x0060 0x02ec 0x057c 3 0
-#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT                 0x0060 0x02ec 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01               0x0060 0x02ec 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT    0x0060 0x02ec 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET          0x0060 0x02ec 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B             0x0060 0x02ec 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL                 0x0064 0x02f0 0x05a4 0 0
-#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2            0x0064 0x02f0 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR             0x0064 0x02f0 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M                0x0064 0x02f0 0x0000 3 0
-#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP                        0x0064 0x02f0 0x066c 4 0
-#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02               0x0064 0x02f0 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00         0x0064 0x02f0 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET         0x0064 0x02f0 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX             0x0064 0x02f0 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX             0x0064 0x02f0 0x0624 8 0
-#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA                 0x0068 0x02f4 0x05a8 0 1
-#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3            0x0068 0x02f4 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC              0x0068 0x02f4 0x0660 2 0
-#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B              0x0068 0x02f4 0x0668 4 0
-#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03               0x0068 0x02f4 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK          0x0068 0x02f4 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK           0x0068 0x02f4 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX             0x0068 0x02f4 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX             0x0068 0x02f4 0x0624 8 1
-#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1           0x006c 0x02f8 0x0574 0 1
-#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT                 0x006c 0x02f8 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR             0x006c 0x02f8 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B           0x006c 0x02f8 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04               0x006c 0x02f8 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN     0x006c 0x02f8 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX             0x006c 0x02f8 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX             0x006c 0x02f8 0x0644 8 2
-#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2           0x0070 0x02fc 0x057c 0 1
-#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT                 0x0070 0x02fc 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID           0x0070 0x02fc 0x04bc 2 0
-#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD                        0x0070 0x02fc 0x0530 3 0
-#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT           0x0070 0x02fc 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05               0x0070 0x02fc 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT    0x0070 0x02fc 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX             0x0070 0x02fc 0x0644 8 3
-#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX             0x0070 0x02fc 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO               0x0074 0x0300 0x0578 0 0
-#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO               0x0074 0x0300 0x0580 1 0
-#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE         0x0074 0x0300 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK                 0x0074 0x0300 0x0000 3 0
-#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP                        0x0074 0x0300 0x069c 4 0
-#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06               0x0074 0x0300 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT                 0x0074 0x0300 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B             0x0074 0x0300 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS            0x0074 0x0300 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS            0x0074 0x0300 0x0620 8 0
-#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC                        0x0078 0x0304 0x0000 0 0
-#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC                        0x0078 0x0304 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE                0x0078 0x0304 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK               0x0078 0x0304 0x0528 3 0
-#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B              0x0078 0x0304 0x0674 4 1
-#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07               0x0078 0x0304 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO07__CCM_STOP                 0x0078 0x0304 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS            0x0078 0x0304 0x0620 8 1
-#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS            0x0078 0x0304 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT                 0x007c 0x0308 0x0000 0 0
-#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B             0x007c 0x0308 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT                        0x007c 0x0308 0x0000 2 0
-#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC                        0x007c 0x0308 0x052c 3 1
-#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT           0x007c 0x0308 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08               0x007c 0x0308 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY             0x007c 0x0308 0x04c0 6 1
-#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS            0x007c 0x0308 0x0640 8 1
-#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS            0x007c 0x0308 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT                 0x0080 0x030c 0x0000 0 0
-#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY           0x0080 0x030c 0x0000 1 0
-#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN                 0x0080 0x030c 0x0618 2 0
-#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC                        0x0080 0x030c 0x0524 3 1
-#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B           0x0080 0x030c 0x0000 4 0
-#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09               0x0080 0x030c 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B           0x0080 0x030c 0x0000 6 0
-#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS            0x0080 0x030c 0x0000 8 0
-#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS            0x0080 0x030c 0x0640 8 2
-#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX          0x0084 0x0310 0x0000 0 0
-#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX          0x0084 0x0310 0x0624 0 2
-#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02         0x0084 0x0310 0x0000 1 0
-#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL              0x0084 0x0310 0x05b4 2 0
-#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02            0x0084 0x0310 0x04c4 3 1
-#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1         0x0084 0x0310 0x0000 4 0
-#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16            0x0084 0x0310 0x0000 5 0
-#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT             0x0084 0x0310 0x0000 8 0
-#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX          0x0088 0x0314 0x0624 0 3
-#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX          0x0088 0x0314 0x0000 0 0
-#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03         0x0088 0x0314 0x0000 1 0
-#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA              0x0088 0x0314 0x05b8 2 0
-#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03            0x0088 0x0314 0x04c8 3 1
-#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK              0x0088 0x0314 0x0594 4 0
-#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17            0x0088 0x0314 0x0000 5 0
-#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN              0x0088 0x0314 0x0618 8 1
-#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS           0x008c 0x0318 0x0000 0 0
-#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS           0x008c 0x0318 0x0620 0 2
-#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK            0x008c 0x0318 0x0000 1 0
-#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP               0x008c 0x0318 0x066c 2 1
-#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04              0x008c 0x0318 0x04d8 3 0
-#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN    0x008c 0x0318 0x0000 4 0
-#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18              0x008c 0x0318 0x0000 5 0
-#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP               0x008c 0x0318 0x069c 8 1
-#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS           0x0090 0x031c 0x0620 0 3
-#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS           0x0090 0x031c 0x0000 0 0
-#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER             0x0090 0x031c 0x0000 1 0
-#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B             0x0090 0x031c 0x0668 2 1
-#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05              0x0090 0x031c 0x04cc 3 1
-#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT   0x0090 0x031c 0x0000 4 0
-#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19              0x0090 0x031c 0x0000 5 0
-#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B             0x0090 0x031c 0x0674 8 2
-#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX          0x0094 0x0320 0x0000 0 0
-#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX          0x0094 0x0320 0x062c 0 0
-#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02         0x0094 0x0320 0x0000 1 0
-#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL              0x0094 0x0320 0x05bc 2 0
-#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06            0x0094 0x0320 0x04dc 3 0
-#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1         0x0094 0x0320 0x058c 4 1
-#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20            0x0094 0x0320 0x0000 5 0
-#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0            0x0094 0x0320 0x0000 8 0
-#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX          0x0098 0x0324 0x062c 0 1
-#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX          0x0098 0x0324 0x0000 0 0
-#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03         0x0098 0x0324 0x0000 1 0
-#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA              0x0098 0x0324 0x05c0 2 0
-#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07            0x0098 0x0324 0x04e0 3 0
-#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2         0x0098 0x0324 0x0590 4 0
-#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21            0x0098 0x0324 0x0000 5 0
-#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE              0x0098 0x0324 0x0000 7 0
-#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK           0x0098 0x0324 0x0554 8 0
-#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS           0x009c 0x0328 0x0000 0 0
-#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS           0x009c 0x0328 0x0628 0 0
-#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS               0x009c 0x0328 0x0000 1 0
-#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX             0x009c 0x0328 0x0000 2 0
-#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08              0x009c 0x0328 0x04e4 3 0
-#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2           0x009c 0x0328 0x0000 4 0
-#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22              0x009c 0x0328 0x0000 5 0
-#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B                        0x009c 0x0328 0x0000 7 0
-#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI             0x009c 0x0328 0x055c 8 0
-#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS           0x00a0 0x032c 0x0628 0 1
-#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS           0x00a0 0x032c 0x0000 0 0
-#define MX6UL_PAD_UART2_RTS_B__ENET1_COL               0x00a0 0x032c 0x0000 1 0
-#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX             0x00a0 0x032c 0x0588 2 0
-#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09              0x00a0 0x032c 0x04e8 3 0
-#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3           0x00a0 0x032c 0x0000 4 0
-#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23              0x00a0 0x032c 0x0000 5 0
-#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL                        0x00a0 0x032c 0x0000 7 0
-#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO             0x00a0 0x032c 0x0558 8 0
-#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX          0x00a4 0x0330 0x0000 0 0
-#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX          0x00a4 0x0330 0x0634 0 0
-#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02         0x00a4 0x0330 0x0000 1 0
-#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD         0x00a4 0x0330 0x0000 2 0
-#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01            0x00a4 0x0330 0x0000 3 0
-#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS         0x00a4 0x0330 0x0000 4 0
-#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS         0x00a4 0x0330 0x0628 4 2
-#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24            0x00a4 0x0330 0x0000 5 0
-#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT          0x00a4 0x0330 0x0000 7 0
-#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID                0x00a4 0x0330 0x04b8 8 1
-#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX          0x00a8 0x0334 0x0634 0 1
-#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX          0x00a8 0x0334 0x0000 0 0
-#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03         0x00a8 0x0334 0x0000 1 0
-#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD         0x00a8 0x0334 0x0000 2 0
-#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00            0x00a8 0x0334 0x0000 3 0
-#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS         0x00a8 0x0334 0x0628 4 3
-#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS         0x00a8 0x0334 0x0000 4 0
-#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25            0x00a8 0x0334 0x0000 5 0
-#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT             0x00a8 0x0334 0x0000 8 0
-#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS           0x00ac 0x0338 0x0000 0 0
-#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS           0x00ac 0x0338 0x0630 0 0
-#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK            0x00ac 0x0338 0x0000 1 0
-#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX             0x00ac 0x0338 0x0000 2 0
-#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10              0x00ac 0x0338 0x0000 3 0
-#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN    0x00ac 0x0338 0x0000 4 0
-#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26              0x00ac 0x0338 0x0000 5 0
-#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT               0x00ac 0x0338 0x0000 8 0
-#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS           0x00b0 0x033c 0x0630 0 1
-#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS           0x00b0 0x033c 0x0000 0 0
-#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER             0x00b0 0x033c 0x0000 1 0
-#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX             0x00b0 0x033c 0x0584 2 0
-#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11              0x00b0 0x033c 0x0000 3 0
-#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT   0x00b0 0x033c 0x0000 4 0
-#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27              0x00b0 0x033c 0x0000 5 0
-#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B            0x00b0 0x033c 0x0000 8 0
-#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX          0x00b4 0x0340 0x0000 0 0
-#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX          0x00b4 0x0340 0x063c 0 0
-#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02         0x00b4 0x0340 0x0000 1 0
-#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL              0x00b4 0x0340 0x05a4 2 1
-#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12            0x00b4 0x0340 0x0000 3 0
-#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02   0x00b4 0x0340 0x0000 4 0
-#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28            0x00b4 0x0340 0x0000 5 0
-#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK           0x00b4 0x0340 0x0544 8 1
-#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX          0x00b8 0x0344 0x063c 0 1
-#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX          0x00b8 0x0344 0x0000 0 0
-#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03         0x00b8 0x0344 0x0000 1 0
-#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA              0x00b8 0x0344 0x05a8 2 2
-#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13            0x00b8 0x0344 0x0000 3 0
-#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01   0x00b8 0x0344 0x0000 4 0
-#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29            0x00b8 0x0344 0x0000 5 0
-#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0            0x00b8 0x0344 0x0000 8 0
-#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30            0x00bc 0x0348 0x0000 5 0
-#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI           0x00bc 0x0348 0x054c 8 0
-#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX          0x00bc 0x0348 0x0000 0 0
-#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX          0x00bc 0x0348 0x0644 0 4
-#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS             0x00bc 0x0348 0x0000 1 0
-#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL              0x00bc 0x0348 0x05ac 2 2
-#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14            0x00bc 0x0348 0x0000 3 0
-#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00   0x00bc 0x0348 0x0000 4 0
-#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX          0x00c0 0x034c 0x0644 0 5
-#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX          0x00c0 0x034c 0x0000 0 0
-#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL             0x00c0 0x034c 0x0000 1 0
-#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA              0x00c0 0x034c 0x05b0 2 2
-#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15            0x00c0 0x034c 0x0000 3 0
-#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB       0x00c0 0x034c 0x0000 4 0
-#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31            0x00c0 0x034c 0x0000 5 0
-#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO           0x00c0 0x034c 0x0548 8 1
-#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00                0x00c4 0x0350 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS                0x00c4 0x0350 0x0638 1 0
-#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS                0x00c4 0x0350 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT             0x00c4 0x0350 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16           0x00c4 0x0350 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX          0x00c4 0x0350 0x0000 4 0
-#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00           0x00c4 0x0350 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00            0x00c4 0x0350 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL          0x00c4 0x0350 0x0000 8 0
-#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01                0x00c8 0x0354 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS                0x00c8 0x0354 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS                0x00c8 0x0354 0x0638 1 1
-#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT             0x00c8 0x0354 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17           0x00c8 0x0354 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX          0x00c8 0x0354 0x0584 4 1
-#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01           0x00c8 0x0354 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00            0x00c8 0x0354 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL          0x00c8 0x0354 0x0000 8 0
-#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN             0x00cc 0x0358 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS           0x00cc 0x0358 0x0640 1 3
-#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS           0x00cc 0x0358 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18              0x00cc 0x0358 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX             0x00cc 0x0358 0x0000 4 0
-#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02              0x00cc 0x0358 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01               0x00cc 0x0358 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT          0x00cc 0x0358 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00                0x00d0 0x035c 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS                0x00d0 0x035c 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                0x00d0 0x035c 0x0640 1 4
-#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19           0x00d0 0x035c 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX          0x00d0 0x035c 0x0588 4 1
-#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03           0x00d0 0x035c 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01            0x00d0 0x035c 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT       0x00d0 0x035c 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01                0x00d4 0x0360 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS                0x00d4 0x0360 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS                0x00d4 0x0360 0x0648 1 2
-#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT             0x00d4 0x0360 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20           0x00d4 0x0360 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO           0x00d4 0x0360 0x0580 4 1
-#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04           0x00d4 0x0360 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02            0x00d4 0x0360 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN             0x00d8 0x0364 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS           0x00d8 0x0364 0x0648 1 3
-#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS           0x00d8 0x0364 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT                        0x00d8 0x0364 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21              0x00d8 0x0364 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC               0x00d8 0x0364 0x0000 4 0
-#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05              0x00d8 0x0364 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02               0x00d8 0x0364 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB    0x00d8 0x0364 0x0000 8 0
-#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK           0x00dc 0x0368 0x0000 0 0
-#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS          0x00dc 0x0368 0x0000 1 0
-#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS          0x00dc 0x0368 0x0650 1 0
-#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT               0x00dc 0x0368 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22             0x00dc 0x0368 0x0000 3 0
-#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1         0x00dc 0x0368 0x0574 4 2
-#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06             0x00dc 0x0368 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03              0x00dc 0x0368 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK               0x00dc 0x0368 0x0594 8 1
-#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER             0x00e0 0x036c 0x0000 0 0
-#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS           0x00e0 0x036c 0x0650 1 1
-#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS           0x00e0 0x036c 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT                        0x00e0 0x036c 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23              0x00e0 0x036c 0x0000 3 0
-#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE                 0x00e0 0x036c 0x0000 4 0
-#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07              0x00e0 0x036c 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03               0x00e0 0x036c 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2           0x00e0 0x036c 0x0590 8 1
-#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00                0x00e4 0x0370 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX         0x00e4 0x0370 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX         0x00e4 0x0370 0x064c 1 1
-#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD      0x00e4 0x0370 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL             0x00e4 0x0370 0x05b4 3 1
-#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO           0x00e4 0x0370 0x0578 4 1
-#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08           0x00e4 0x0370 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04            0x00e4 0x0370 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR         0x00e4 0x0370 0x0000 8 0
-#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01                0x00e8 0x0374 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX         0x00e8 0x0374 0x064c 1 2
-#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX         0x00e8 0x0374 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK       0x00e8 0x0374 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA             0x00e8 0x0374 0x05b8 3 1
-#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC            0x00e8 0x0374 0x0000 4 0
-#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09           0x00e8 0x0374 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04            0x00e8 0x0374 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC          0x00e8 0x0374 0x0664 8 1
-#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN             0x00ec 0x0378 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX            0x00ec 0x0378 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX            0x00ec 0x0378 0x0654 1 0
-#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B                0x00ec 0x0378 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL                        0x00ec 0x0378 0x05bc 3 1
-#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26              0x00ec 0x0378 0x0000 4 0
-#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10              0x00ec 0x0378 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05               0x00ec 0x0378 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M       0x00ec 0x0378 0x0000 8 0
-#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00                0x00f0 0x037c 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX         0x00f0 0x037c 0x0654 1 1
-#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX         0x00f0 0x037c 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN      0x00f0 0x037c 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA             0x00f0 0x037c 0x05c0 3 1
-#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02           0x00f0 0x037c 0x0000 4 0
-#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11           0x00f0 0x037c 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05            0x00f0 0x037c 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01                0x00f4 0x0380 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX         0x00f4 0x0380 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX         0x00f4 0x0380 0x065c 1 0
-#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD      0x00f4 0x0380 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK          0x00f4 0x0380 0x0564 3 0
-#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03           0x00f4 0x0380 0x0000 4 0
-#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12           0x00f4 0x0380 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06            0x00f4 0x0380 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR         0x00f4 0x0380 0x0000 8 0
-#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN             0x00f8 0x0384 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX            0x00f8 0x0384 0x065c 1 1
-#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX            0x00f8 0x0384 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK          0x00f8 0x0384 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI             0x00f8 0x0384 0x056c 3 0
-#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN                0x00f8 0x0384 0x0000 4 0
-#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13              0x00f8 0x0384 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06               0x00f8 0x0384 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC             0x00f8 0x0384 0x0660 8 1
-#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK           0x00fc 0x0388 0x0000 0 0
-#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS          0x00fc 0x0388 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS          0x00fc 0x0388 0x0658 1 0
-#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B       0x00fc 0x0388 0x0000 2 0
-#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO            0x00fc 0x0388 0x0568 3 0
-#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2         0x00fc 0x0388 0x057c 4 2
-#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14             0x00fc 0x0388 0x0000 5 0
-#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07              0x00fc 0x0388 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID         0x00fc 0x0388 0x04bc 8 1
-#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER             0x0100 0x038c 0x0000 0 0
-#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS           0x0100 0x038c 0x0658 1 1
-#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS           0x0100 0x038c 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN         0x0100 0x038c 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0              0x0100 0x038c 0x0000 3 0
-#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25              0x0100 0x038c 0x0000 4 0
-#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15              0x0100 0x038c 0x0000 5 0
-#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07               0x0100 0x038c 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY          0x0100 0x038c 0x0000 8 0
-#define MX6UL_PAD_LCD_CLK__LCDIF_CLK                   0x0104 0x0390 0x0000 0 0
-#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN                        0x0104 0x0390 0x0000 1 0
-#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX                        0x0104 0x0390 0x0000 2 0
-#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX                        0x0104 0x0390 0x063c 2 2
-#define MX6UL_PAD_LCD_CLK__SAI3_MCLK                   0x0104 0x0390 0x0000 3 0
-#define MX6UL_PAD_LCD_CLK__EIM_CS2_B                   0x0104 0x0390 0x0000 4 0
-#define MX6UL_PAD_LCD_CLK__GPIO3_IO00                  0x0104 0x0390 0x0000 5 0
-#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                0x0104 0x0390 0x0000 8 0
-#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE             0x0108 0x0394 0x0000 0 0
-#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E               0x0108 0x0394 0x0000 1 0
-#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX             0x0108 0x0394 0x063c 2 3
-#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX             0x0108 0x0394 0x0000 2 0
-#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC             0x0108 0x0394 0x060c 3 0
-#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B                        0x0108 0x0394 0x0000 4 0
-#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01               0x0108 0x0394 0x0000 5 0
-#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY               0x0108 0x0394 0x0000 8 0
-#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC               0x010c 0x0398 0x05dc 0 0
-#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS                  0x010c 0x0398 0x0000 1 0
-#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS             0x010c 0x0398 0x0000 2 0
-#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS             0x010c 0x0398 0x0638 2 2
-#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK              0x010c 0x0398 0x0608 3 0
-#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB      0x010c 0x0398 0x0000 4 0
-#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02                        0x010c 0x0398 0x0000 5 0
-#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1                        0x010c 0x0398 0x0000 8 0
-#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC               0x0110 0x039c 0x0000 0 0
-#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY                        0x0110 0x039c 0x05dc 1 1
-#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS             0x0110 0x039c 0x0638 2 3
-#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS             0x0110 0x039c 0x0000 2 0
-#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA              0x0110 0x039c 0x0000 3 0
-#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B              0x0110 0x039c 0x0000 4 0
-#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03                        0x0110 0x039c 0x0000 5 0
-#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2                        0x0110 0x039c 0x0000 8 0
-#define MX6UL_PAD_LCD_RESET__LCDIF_RESET               0x0114 0x03a0 0x0000 0 0
-#define MX6UL_PAD_LCD_RESET__LCDIF_CS                  0x0114 0x03a0 0x0000 1 0
-#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI          0x0114 0x03a0 0x0000 2 0
-#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA              0x0114 0x03a0 0x0000 3 0
-#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY            0x0114 0x03a0 0x0000 4 0
-#define MX6UL_PAD_LCD_RESET__GPIO3_IO04                        0x0114 0x03a0 0x0000 5 0
-#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3                        0x0114 0x03a0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00             0x0118 0x03a4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA00__PWM1_OUT                 0x0118 0x03a4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN     0x0118 0x03a4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA00__I2C3_SDA                 0x0118 0x03a4 0x05b8 4 2
-#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05               0x0118 0x03a4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00             0x0118 0x03a4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK                        0x0118 0x03a4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01             0x011c 0x03a8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA01__PWM2_OUT                 0x011c 0x03a8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT    0x011c 0x03a8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA01__I2C3_SCL                 0x011c 0x03a8 0x05b4 4 2
-#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06               0x011c 0x03a8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01             0x011c 0x03a8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC             0x011c 0x03a8 0x05ec 8 0
-#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02             0x0120 0x03ac 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA02__PWM3_OUT                 0x0120 0x03ac 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN     0x0120 0x03ac 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA02__I2C4_SDA                 0x0120 0x03ac 0x05c0 4 2
-#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07               0x0120 0x03ac 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02             0x0120 0x03ac 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK             0x0120 0x03ac 0x05e8 8 0
-#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03             0x0124 0x03b0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA03__PWM4_OUT                 0x0124 0x03b0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT    0x0124 0x03b0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA03__I2C4_SCL                 0x0124 0x03b0 0x05bc 4 2
-#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08               0x0124 0x03b0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03             0x0124 0x03b0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA             0x0124 0x03b0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04             0x0128 0x03b4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS            0x0128 0x03b4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS            0x0128 0x03b4 0x0658 1 2
-#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN     0x0128 0x03b4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK             0x0128 0x03b4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09               0x0128 0x03b4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04             0x0128 0x03b4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA             0x0128 0x03b4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05             0x012c 0x03b8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS            0x012c 0x03b8 0x0658 1 3
-#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS            0x012c 0x03b8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT    0x012c 0x03b8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT                        0x012c 0x03b8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10               0x012c 0x03b8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05             0x012c 0x03b8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1               0x012c 0x03b8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06             0x0130 0x03bc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS            0x0130 0x03bc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS            0x0130 0x03bc 0x0650 1 2
-#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN     0x0130 0x03bc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK               0x0130 0x03bc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11               0x0130 0x03bc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06             0x0130 0x03bc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2               0x0130 0x03bc 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07             0x0134 0x03c0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS            0x0134 0x03c0 0x0650 1 3
-#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS            0x0134 0x03c0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT    0x0134 0x03c0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK            0x0134 0x03c0 0x061c 4 0
-#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12               0x0134 0x03c0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07             0x0134 0x03c0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3               0x0134 0x03c0 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08             0x0138 0x03c4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA08__SPDIF_IN                 0x0138 0x03c4 0x0618 1 2
-#define MX6UL_PAD_LCD_DATA08__CSI_DATA16               0x0138 0x03c4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA08__EIM_DATA00               0x0138 0x03c4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13               0x0138 0x03c4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08             0x0138 0x03c4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX              0x0138 0x03c4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09             0x013c 0x03c8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK                        0x013c 0x03c8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA09__CSI_DATA17               0x013c 0x03c8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA09__EIM_DATA01               0x013c 0x03c8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14               0x013c 0x03c8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09             0x013c 0x03c8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX              0x013c 0x03c8 0x0584 8 2
-#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10             0x0140 0x03cc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC             0x0140 0x03cc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA10__CSI_DATA18               0x0140 0x03cc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA10__EIM_DATA02               0x0140 0x03cc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15               0x0140 0x03cc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10             0x0140 0x03cc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX              0x0140 0x03cc 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11             0x0144 0x03d0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK             0x0144 0x03d0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA11__CSI_DATA19               0x0144 0x03d0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA11__EIM_DATA03               0x0144 0x03d0 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16               0x0144 0x03d0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11             0x0144 0x03d0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX              0x0144 0x03d0 0x0588 8 2
-#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12             0x0148 0x03d4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC             0x0148 0x03d4 0x060c 1 1
-#define MX6UL_PAD_LCD_DATA12__CSI_DATA20               0x0148 0x03d4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA12__EIM_DATA04               0x0148 0x03d4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17               0x0148 0x03d4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12             0x0148 0x03d4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY               0x0148 0x03d4 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13             0x014c 0x03d8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK             0x014c 0x03d8 0x0608 1 1
-#define MX6UL_PAD_LCD_DATA13__CSI_DATA21               0x014c 0x03d8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA13__EIM_DATA05               0x014c 0x03d8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18               0x014c 0x03d8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13             0x014c 0x03d8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B           0x014c 0x03d8 0x0000 8 0
-#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14             0x0150 0x03dc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA             0x0150 0x03dc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA14__CSI_DATA22               0x0150 0x03dc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA14__EIM_DATA06               0x0150 0x03dc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19               0x0150 0x03dc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14             0x0150 0x03dc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4             0x0150 0x03dc 0x068c 8 0
-#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15             0x0154 0x03e0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA             0x0154 0x03e0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA15__CSI_DATA23               0x0154 0x03e0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA15__EIM_DATA07               0x0154 0x03e0 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20               0x0154 0x03e0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15             0x0154 0x03e0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5             0x0154 0x03e0 0x0690 8 0
-#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16             0x0158 0x03e4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX             0x0158 0x03e4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX             0x0158 0x03e4 0x0654 1 2
-#define MX6UL_PAD_LCD_DATA16__CSI_DATA01               0x0158 0x03e4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA16__EIM_DATA08               0x0158 0x03e4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21               0x0158 0x03e4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24             0x0158 0x03e4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6             0x0158 0x03e4 0x0694 8 0
-#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17             0x015c 0x03e8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX             0x015c 0x03e8 0x0654 1 3
-#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX             0x015c 0x03e8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA17__CSI_DATA00               0x015c 0x03e8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA17__EIM_DATA09               0x015c 0x03e8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22               0x015c 0x03e8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25             0x015c 0x03e8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7             0x015c 0x03e8 0x0698 8 0
-#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18             0x0160 0x03ec 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA18__PWM5_OUT                 0x0160 0x03ec 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO         0x0160 0x03ec 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA18__CSI_DATA10               0x0160 0x03ec 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA18__EIM_DATA10               0x0160 0x03ec 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23               0x0160 0x03ec 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26             0x0160 0x03ec 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD               0x0160 0x03ec 0x0678 8 1
-#define MX6UL_PAD_LCD_DATA19__EIM_DATA11               0x0164 0x03f0 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24               0x0164 0x03f0 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27             0x0164 0x03f0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK               0x0164 0x03f0 0x0670 8 1
-#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19             0x0164 0x03f0 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA19__PWM6_OUT                 0x0164 0x03f0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY           0x0164 0x03f0 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA19__CSI_DATA11               0x0164 0x03f0 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA20__EIM_DATA12               0x0168 0x03f4 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25               0x0168 0x03f4 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28             0x0168 0x03f4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0             0x0168 0x03f4 0x067c 8 1
-#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20             0x0168 0x03f4 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX             0x0168 0x03f4 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX             0x0168 0x03f4 0x065c 1 2
-#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK              0x0168 0x03f4 0x0534 2 0
-#define MX6UL_PAD_LCD_DATA20__CSI_DATA12               0x0168 0x03f4 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21             0x016c 0x03f8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX             0x016c 0x03f8 0x065c 1 3
-#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX             0x016c 0x03f8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0               0x016c 0x03f8 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA21__CSI_DATA13               0x016c 0x03f8 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA21__EIM_DATA13               0x016c 0x03f8 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26               0x016c 0x03f8 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29             0x016c 0x03f8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1             0x016c 0x03f8 0x0680 8 1
-#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22             0x0170 0x03fc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT                        0x0170 0x03fc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI              0x0170 0x03fc 0x053c 2 0
-#define MX6UL_PAD_LCD_DATA22__CSI_DATA14               0x0170 0x03fc 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA22__EIM_DATA14               0x0170 0x03fc 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27               0x0170 0x03fc 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30             0x0170 0x03fc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2             0x0170 0x03fc 0x0684 8 0
-#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23             0x0174 0x0400 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA23__MQS_LEFT                 0x0174 0x0400 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO              0x0174 0x0400 0x0538 2 0
-#define MX6UL_PAD_LCD_DATA23__CSI_DATA15               0x0174 0x0400 0x0000 3 0
-#define MX6UL_PAD_LCD_DATA23__EIM_DATA15               0x0174 0x0400 0x0000 4 0
-#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28               0x0174 0x0400 0x0000 5 0
-#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31             0x0174 0x0400 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3             0x0174 0x0400 0x0688 8 1
-#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B              0x0178 0x0404 0x0000 0 0
-#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK                        0x0178 0x0404 0x0670 1 2
-#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK               0x0178 0x0404 0x0000 2 0
-#define MX6UL_PAD_NAND_RE_B__KPP_ROW00                 0x0178 0x0404 0x0000 3 0
-#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00                        0x0178 0x0404 0x0000 4 0
-#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00                        0x0178 0x0404 0x0000 5 0
-#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2                        0x0178 0x0404 0x0000 8 0
-#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B              0x017c 0x0408 0x0000 0 0
-#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD                        0x017c 0x0408 0x0678 1 2
-#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B              0x017c 0x0408 0x0000 2 0
-#define MX6UL_PAD_NAND_WE_B__KPP_COL00                 0x017c 0x0408 0x0000 3 0
-#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01                        0x017c 0x0408 0x0000 4 0
-#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01                        0x017c 0x0408 0x0000 5 0
-#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3                        0x017c 0x0408 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00          0x0180 0x040c 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0            0x0180 0x040c 0x067c 1 2
-#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B            0x0180 0x040c 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA00__KPP_ROW01               0x0180 0x040c 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA00__EIM_AD08                        0x0180 0x040c 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02              0x0180 0x040c 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY              0x0180 0x040c 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01          0x0184 0x0410 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1            0x0184 0x0410 0x0680 1 2
-#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS              0x0184 0x0410 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA01__KPP_COL01               0x0184 0x0410 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA01__EIM_AD09                        0x0184 0x0410 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03              0x0184 0x0410 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1              0x0184 0x0410 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02          0x0188 0x0414 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2            0x0188 0x0414 0x0684 1 1
-#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00           0x0188 0x0414 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA02__KPP_ROW02               0x0188 0x0414 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA02__EIM_AD10                        0x0188 0x0414 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04              0x0188 0x0414 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2              0x0188 0x0414 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03          0x018c 0x0418 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3            0x018c 0x0418 0x0688 1 2
-#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01           0x018c 0x0418 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA03__KPP_COL02               0x018c 0x0418 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA03__EIM_AD11                        0x018c 0x0418 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05              0x018c 0x0418 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3              0x018c 0x0418 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04          0x0190 0x041c 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4            0x0190 0x041c 0x068c 1 1
-#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02           0x0190 0x041c 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK             0x0190 0x041c 0x0564 3 1
-#define MX6UL_PAD_NAND_DATA04__EIM_AD12                        0x0190 0x041c 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06              0x0190 0x041c 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX            0x0190 0x041c 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX            0x0190 0x041c 0x062c 8 2
-#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05          0x0194 0x0420 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5            0x0194 0x0420 0x0690 1 1
-#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03           0x0194 0x0420 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI             0x0194 0x0420 0x056c 3 1
-#define MX6UL_PAD_NAND_DATA05__EIM_AD13                        0x0194 0x0420 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07              0x0194 0x0420 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX            0x0194 0x0420 0x062c 8 3
-#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX            0x0194 0x0420 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06          0x0198 0x0424 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6            0x0198 0x0424 0x0694 1 1
-#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK            0x0198 0x0424 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO             0x0198 0x0424 0x0568 3 1
-#define MX6UL_PAD_NAND_DATA06__EIM_AD14                        0x0198 0x0424 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08              0x0198 0x0424 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS           0x0198 0x0424 0x0000 8 0
-#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS           0x0198 0x0424 0x0628 8 4
-#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07          0x019c 0x0428 0x0000 0 0
-#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7            0x019c 0x0428 0x0698 1 1
-#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B            0x019c 0x0428 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0              0x019c 0x0428 0x0000 3 0
-#define MX6UL_PAD_NAND_DATA07__EIM_AD15                        0x019c 0x0428 0x0000 4 0
-#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09              0x019c 0x0428 0x0000 5 0
-#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS           0x019c 0x0428 0x0628 8 5
-#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS           0x019c 0x0428 0x0000 8 0
-#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE                        0x01a0 0x042c 0x0000 0 0
-#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B             0x01a0 0x042c 0x0000 1 0
-#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS                 0x01a0 0x042c 0x0000 2 0
-#define MX6UL_PAD_NAND_ALE__PWM3_OUT                   0x01a0 0x042c 0x0000 3 0
-#define MX6UL_PAD_NAND_ALE__EIM_ADDR17                 0x01a0 0x042c 0x0000 4 0
-#define MX6UL_PAD_NAND_ALE__GPIO4_IO10                 0x01a0 0x042c 0x0000 5 0
-#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1                 0x01a0 0x042c 0x0000 8 0
-#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B              0x01a4 0x0430 0x0000 0 0
-#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B            0x01a4 0x0430 0x0000 1 0
-#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK               0x01a4 0x0430 0x0000 2 0
-#define MX6UL_PAD_NAND_WP_B__PWM4_OUT                  0x01a4 0x0430 0x0000 3 0
-#define MX6UL_PAD_NAND_WP_B__EIM_BCLK                  0x01a4 0x0430 0x0000 4 0
-#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11                        0x01a4 0x0430 0x0000 5 0
-#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY                        0x01a4 0x0430 0x0000 8 0
-#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B                0x01a8 0x0434 0x0000 0 0
-#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4           0x01a8 0x0434 0x0000 1 0
-#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00          0x01a8 0x0434 0x0000 2 0
-#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0             0x01a8 0x0434 0x0000 3 0
-#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B              0x01a8 0x0434 0x0000 4 0
-#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12             0x01a8 0x0434 0x0000 5 0
-#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX           0x01a8 0x0434 0x0000 8 0
-#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX           0x01a8 0x0434 0x0634 8 2
-#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B            0x01ac 0x0438 0x0000 0 0
-#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5             0x01ac 0x0438 0x0000 1 0
-#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01            0x01ac 0x0438 0x0000 2 0
-#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK              0x01ac 0x0438 0x0554 3 1
-#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B              0x01ac 0x0438 0x0000 4 0
-#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13               0x01ac 0x0438 0x0000 5 0
-#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX             0x01ac 0x0438 0x0634 8 3
-#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX             0x01ac 0x0438 0x0000 8 0
-#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B            0x01b0 0x043c 0x0000 0 0
-#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6             0x01b0 0x043c 0x0000 1 0
-#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02            0x01b0 0x043c 0x0000 2 0
-#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI              0x01b0 0x043c 0x055c 3 1
-#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18               0x01b0 0x043c 0x0000 4 0
-#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14               0x01b0 0x043c 0x0000 5 0
-#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS            0x01b0 0x043c 0x0000 8 0
-#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS            0x01b0 0x043c 0x0630 8 2
-#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE                        0x01b4 0x0440 0x0000 0 0
-#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7               0x01b4 0x0440 0x0000 1 0
-#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03              0x01b4 0x0440 0x0000 2 0
-#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO                        0x01b4 0x0440 0x0558 3 1
-#define MX6UL_PAD_NAND_CLE__EIM_ADDR16                 0x01b4 0x0440 0x0000 4 0
-#define MX6UL_PAD_NAND_CLE__GPIO4_IO15                 0x01b4 0x0440 0x0000 5 0
-#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS              0x01b4 0x0440 0x0630 8 3
-#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS              0x01b4 0x0440 0x0000 8 0
-#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS                        0x01b8 0x0444 0x0000 0 0
-#define MX6UL_PAD_NAND_DQS__CSI_FIELD                  0x01b8 0x0444 0x0530 1 1
-#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B               0x01b8 0x0444 0x0000 2 0
-#define MX6UL_PAD_NAND_DQS__PWM5_OUT                   0x01b8 0x0444 0x0000 3 0
-#define MX6UL_PAD_NAND_DQS__EIM_WAIT                   0x01b8 0x0444 0x0000 4 0
-#define MX6UL_PAD_NAND_DQS__GPIO4_IO16                 0x01b8 0x0444 0x0000 5 0
-#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01           0x01b8 0x0444 0x0000 6 0
-#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK              0x01b8 0x0444 0x061c 8 1
-#define MX6UL_PAD_SD1_CMD__USDHC1_CMD                  0x01bc 0x0448 0x0000 0 0
-#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1               0x01bc 0x0448 0x0000 1 0
-#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC                        0x01bc 0x0448 0x0000 2 0
-#define MX6UL_PAD_SD1_CMD__SPDIF_OUT                   0x01bc 0x0448 0x0000 3 0
-#define MX6UL_PAD_SD1_CMD__EIM_ADDR19                  0x01bc 0x0448 0x0000 4 0
-#define MX6UL_PAD_SD1_CMD__GPIO2_IO16                  0x01bc 0x0448 0x0000 5 0
-#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00            0x01bc 0x0448 0x0000 6 0
-#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR                        0x01bc 0x0448 0x0000 8 0
-#define MX6UL_PAD_SD1_CLK__USDHC1_CLK                  0x01c0 0x044c 0x0000 0 0
-#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2               0x01c0 0x044c 0x0000 1 0
-#define MX6UL_PAD_SD1_CLK__SAI2_MCLK                   0x01c0 0x044c 0x0000 2 0
-#define MX6UL_PAD_SD1_CLK__SPDIF_IN                    0x01c0 0x044c 0x0618 3 3
-#define MX6UL_PAD_SD1_CLK__EIM_ADDR20                  0x01c0 0x044c 0x0000 4 0
-#define MX6UL_PAD_SD1_CLK__GPIO2_IO17                  0x01c0 0x044c 0x0000 5 0
-#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC                 0x01c0 0x044c 0x0664 8 2
-#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0              0x01c4 0x0450 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3             0x01c4 0x0450 0x0000 1 0
-#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC              0x01c4 0x0450 0x05fc 2 1
-#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX               0x01c4 0x0450 0x0000 3 0
-#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21                        0x01c4 0x0450 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18                        0x01c4 0x0450 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID            0x01c4 0x0450 0x04b8 8 2
-#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1              0x01c8 0x0454 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA1__GPT2_CLK                  0x01c8 0x0454 0x05a0 1 1
-#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK              0x01c8 0x0454 0x05f8 2 1
-#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX               0x01c8 0x0454 0x0584 3 3
-#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22                        0x01c8 0x0454 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19                        0x01c8 0x0454 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR              0x01c8 0x0454 0x0000 8 0
-#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2              0x01cc 0x0458 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1             0x01cc 0x0458 0x0598 1 1
-#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA              0x01cc 0x0458 0x05f4 2 1
-#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX               0x01cc 0x0458 0x0000 3 0
-#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23                        0x01cc 0x0458 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20                        0x01cc 0x0458 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1                 0x01cc 0x0458 0x0000 6 0
-#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC               0x01cc 0x0458 0x0660 8 2
-#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3              0x01d0 0x045c 0x0000 0 0
-#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2             0x01d0 0x045c 0x059c 1 1
-#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA              0x01d0 0x045c 0x0000 2 0
-#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX               0x01d0 0x045c 0x0588 3 3
-#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24                        0x01d0 0x045c 0x0000 4 0
-#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21                        0x01d0 0x045c 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2                 0x01d0 0x045c 0x0000 6 0
-#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID            0x01d0 0x045c 0x04bc 8 2
-#define MX6UL_PAD_CSI_MCLK__CSI_MCLK                   0x01d4 0x0460 0x0000 0 0
-#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B                        0x01d4 0x0460 0x0674 1 0
-#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B              0x01d4 0x0460 0x0000 2 0
-#define MX6UL_PAD_CSI_MCLK__I2C1_SDA                   0x01d4 0x0460 0x05a8 3 0
-#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B                  0x01d4 0x0460 0x0000 4 0
-#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17                 0x01d4 0x0460 0x0000 5 0
-#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL          0x01d4 0x0460 0x0000 6 0
-#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX               0x01d4 0x0460 0x0000 8 0
-#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX               0x01d4 0x0460 0x064c 8 0
-#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK               0x01d8 0x0464 0x0528 0 1
-#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP                        0x01d8 0x0464 0x069c 1 2
-#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B            0x01d8 0x0464 0x0000 2 0
-#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL                 0x01d8 0x0464 0x05a4 3 2
-#define MX6UL_PAD_CSI_PIXCLK__EIM_OE                   0x01d8 0x0464 0x0000 4 0
-#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18               0x01d8 0x0464 0x0000 5 0
-#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5            0x01d8 0x0464 0x0000 6 0
-#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX             0x01d8 0x0464 0x064c 8 3
-#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX             0x01d8 0x0464 0x0000 8 0
-#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC                 0x01dc 0x0468 0x052c 0 0
-#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK                        0x01dc 0x0468 0x0670 1 0
-#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK            0x01dc 0x0468 0x0000 2 0
-#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA                  0x01dc 0x0468 0x05b0 3 0
-#define MX6UL_PAD_CSI_VSYNC__EIM_RW                    0x01dc 0x0468 0x0000 4 0
-#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19                        0x01dc 0x0468 0x0000 5 0
-#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT                  0x01dc 0x0468 0x0000 6 0
-#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS             0x01dc 0x0468 0x0648 8 0
-#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS             0x01dc 0x0468 0x0000 8 0
-#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC                 0x01e0 0x046c 0x0524 0 0
-#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD                        0x01e0 0x046c 0x0678 1 0
-#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD             0x01e0 0x046c 0x0000 2 0
-#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL                  0x01e0 0x046c 0x05ac 3 0
-#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B                 0x01e0 0x046c 0x0000 4 0
-#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20                        0x01e0 0x046c 0x0000 5 0
-#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT                  0x01e0 0x046c 0x0000 6 0
-#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS             0x01e0 0x046c 0x0000 8 0
-#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS             0x01e0 0x046c 0x0648 8 1
-#define MX6UL_PAD_CSI_DATA00__CSI_DATA02               0x01e4 0x0470 0x04c4 0 0
-#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0             0x01e4 0x0470 0x067c 1 0
-#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B         0x01e4 0x0470 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK              0x01e4 0x0470 0x0544 3 0
-#define MX6UL_PAD_CSI_DATA00__EIM_AD00                 0x01e4 0x0470 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21               0x01e4 0x0470 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT             0x01e4 0x0470 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX             0x01e4 0x0470 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX             0x01e4 0x0470 0x0644 8 0
-#define MX6UL_PAD_CSI_DATA01__CSI_DATA03               0x01e8 0x0474 0x04c8 0 0
-#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1             0x01e8 0x0474 0x0680 1 0
-#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN          0x01e8 0x0474 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0               0x01e8 0x0474 0x0000 3 0
-#define MX6UL_PAD_CSI_DATA01__EIM_AD01                 0x01e8 0x0474 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22               0x01e8 0x0474 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK                        0x01e8 0x0474 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX             0x01e8 0x0474 0x0644 8 1
-#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX             0x01e8 0x0474 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA02__CSI_DATA04               0x01ec 0x0478 0x04d8 0 1
-#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2             0x01ec 0x0478 0x0684 1 2
-#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD          0x01ec 0x0478 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI              0x01ec 0x0478 0x054c 3 1
-#define MX6UL_PAD_CSI_DATA02__EIM_AD02                 0x01ec 0x0478 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23               0x01ec 0x0478 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC             0x01ec 0x0478 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS            0x01ec 0x0478 0x0640 8 5
-#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS            0x01ec 0x0478 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA03__CSI_DATA05               0x01f0 0x047c 0x04cc 0 0
-#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3             0x01f0 0x047c 0x0688 1 0
-#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD            0x01f0 0x047c 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO              0x01f0 0x047c 0x0548 3 0
-#define MX6UL_PAD_CSI_DATA03__EIM_AD03                 0x01f0 0x047c 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24               0x01f0 0x047c 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK             0x01f0 0x047c 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS            0x01f0 0x047c 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS            0x01f0 0x047c 0x0640 8 0
-#define MX6UL_PAD_CSI_DATA04__CSI_DATA06               0x01f4 0x0480 0x04dc 0 1
-#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4             0x01f4 0x0480 0x068c 1 2
-#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK           0x01f4 0x0480 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK              0x01f4 0x0480 0x0534 3 1
-#define MX6UL_PAD_CSI_DATA04__EIM_AD04                 0x01f4 0x0480 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25               0x01f4 0x0480 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC             0x01f4 0x0480 0x05ec 6 1
-#define MX6UL_PAD_CSI_DATA04__USDHC1_WP                        0x01f4 0x0480 0x066c 8 2
-#define MX6UL_PAD_CSI_DATA05__CSI_DATA07               0x01f8 0x0484 0x04e0 0 1
-#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5             0x01f8 0x0484 0x0690 1 2
-#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B         0x01f8 0x0484 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0               0x01f8 0x0484 0x0000 3 0
-#define MX6UL_PAD_CSI_DATA05__EIM_AD05                 0x01f8 0x0484 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26               0x01f8 0x0484 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK             0x01f8 0x0484 0x05e8 6 1
-#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B              0x01f8 0x0484 0x0668 8 2
-#define MX6UL_PAD_CSI_DATA06__CSI_DATA08               0x01fc 0x0488 0x04e4 0 1
-#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6             0x01fc 0x0488 0x0694 1 2
-#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN          0x01fc 0x0488 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI              0x01fc 0x0488 0x053c 3 1
-#define MX6UL_PAD_CSI_DATA06__EIM_AD06                 0x01fc 0x0488 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27               0x01fc 0x0488 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA             0x01fc 0x0488 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B           0x01fc 0x0488 0x0000 8 0
-#define MX6UL_PAD_CSI_DATA07__CSI_DATA09               0x0200 0x048c 0x04e8 0 1
-#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7             0x0200 0x048c 0x0698 1 2
-#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD          0x0200 0x048c 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO              0x0200 0x048c 0x0538 3 1
-#define MX6UL_PAD_CSI_DATA07__EIM_AD07                 0x0200 0x048c 0x0000 4 0
-#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28               0x0200 0x048c 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA             0x0200 0x048c 0x0000 6 0
-#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT           0x0200 0x048c 0x0000 8 0
+#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10                          0x0014 0x02A0 0x0000 0x5 0x0
+#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11                          0x0018 0x02A4 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00                        0x001C 0x02A8 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01                        0x0020 0x02AC 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02                        0x0024 0x02B0 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03                        0x0028 0x02B4 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04                        0x002C 0x02B8 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05                        0x0030 0x02BC 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06                        0x0034 0x02C0 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07                        0x0038 0x02C4 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08                        0x003C 0x02C8 0x0000 0x5 0x0
+#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09                        0x0040 0x02CC 0x0000 0x5 0x0
+#define MX6UL_PAD_JTAG_MOD__SJC_MOD                               0x0044 0x02D0 0x0000 0x0 0x0
+#define MX6UL_PAD_JTAG_MOD__GPT2_CLK                              0x0044 0x02D0 0x05A0 0x1 0x0
+#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT                             0x0044 0x02D0 0x0000 0x2 0x0
+#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M                     0x0044 0x02D0 0x0000 0x3 0x0
+#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY                          0x0044 0x02D0 0x04C0 0x4 0x0
+#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10                            0x0044 0x02D0 0x0000 0x5 0x0
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00                      0x0044 0x02D0 0x0610 0x6 0x0
+#define MX6UL_PAD_JTAG_TMS__SJC_TMS                               0x0048 0x02D4 0x0000 0x0 0x0
+#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1                         0x0048 0x02D4 0x0598 0x1 0x0
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK                             0x0048 0x02D4 0x05F0 0x2 0x0
+#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1                             0x0048 0x02D4 0x0000 0x3 0x0
+#define MX6UL_PAD_JTAG_TMS__CCM_WAIT                              0x0048 0x02D4 0x0000 0x4 0x0
+#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11                            0x0048 0x02D4 0x0000 0x5 0x0
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01                      0x0048 0x02D4 0x0614 0x6 0x0
+#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT                             0x0048 0x02D4 0x0000 0x8 0x0
+#define MX6UL_PAD_JTAG_TDO__SJC_TDO                               0x004C 0x02D8 0x0000 0x0 0x0
+#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2                         0x004C 0x02D8 0x059C 0x1 0x0
+#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC                          0x004C 0x02D8 0x05FC 0x2 0x0
+#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2                             0x004C 0x02D8 0x0000 0x3 0x0
+#define MX6UL_PAD_JTAG_TDO__CCM_STOP                              0x004C 0x02D8 0x0000 0x4 0x0
+#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12                            0x004C 0x02D8 0x0000 0x5 0x0
+#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT                             0x004C 0x02D8 0x0000 0x6 0x0
+#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT                             0x004C 0x02D8 0x0000 0x8 0x0
+#define MX6UL_PAD_JTAG_TDI__SJC_TDI                               0x0050 0x02DC 0x0000 0x0 0x0
+#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1                         0x0050 0x02DC 0x0000 0x1 0x0
+#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK                          0x0050 0x02DC 0x05F8 0x2 0x0
+#define MX6UL_PAD_JTAG_TDI__PWM6_OUT                              0x0050 0x02DC 0x0000 0x4 0x0
+#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13                            0x0050 0x02DC 0x0000 0x5 0x0
+#define MX6UL_PAD_JTAG_TDI__MQS_LEFT                              0x0050 0x02DC 0x0000 0x6 0x0
+#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL                       0x0050 0x02DC 0x0000 0x8 0x0
+#define MX6UL_PAD_JTAG_TCK__SJC_TCK                               0x0054 0x02E0 0x0000 0x0 0x0
+#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2                         0x0054 0x02E0 0x0000 0x1 0x0
+#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA                          0x0054 0x02E0 0x05F4 0x2 0x0
+#define MX6UL_PAD_JTAG_TCK__PWM7_OUT                              0x0054 0x02E0 0x0000 0x4 0x0
+#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14                            0x0054 0x02E0 0x0000 0x5 0x0
+#define MX6UL_PAD_JTAG_TCK__REF_CLK_32K                           0x0054 0x02E0 0x0000 0x6 0x0
+#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL                       0x0054 0x02E0 0x0000 0x8 0x0
+#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB                          0x0058 0x02E4 0x0000 0x0 0x0
+#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3                      0x0058 0x02E4 0x0000 0x1 0x0
+#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA                       0x0058 0x02E4 0x0000 0x2 0x0
+#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT                           0x0058 0x02E4 0x0000 0x4 0x0
+#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15                         0x0058 0x02E4 0x0000 0x5 0x0
+#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M                        0x0058 0x02E4 0x0000 0x6 0x0
+#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS                   0x0058 0x02E4 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL                            0x005C 0x02E8 0x05AC 0x0 0x1
+#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1                       0x005C 0x02E8 0x058C 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID                      0x005C 0x02E8 0x04B8 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1                      0x005C 0x02E8 0x0574 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT                           0x005C 0x02E8 0x0000 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00                          0x005C 0x02E8 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN                0x005C 0x02E8 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET                    0x005C 0x02E8 0x0000 0x7 0x0
+#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B                        0x005C 0x02E8 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA                            0x0060 0x02EC 0x05B0 0x0 0x1
+#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1                       0x0060 0x02EC 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC                         0x0060 0x02EC 0x0664 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2                      0x0060 0x02EC 0x057C 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT                            0x0060 0x02EC 0x0000 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                          0x0060 0x02EC 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT               0x0060 0x02EC 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET                     0x0060 0x02EC 0x0000 0x7 0x0
+#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B                        0x0060 0x02EC 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL                            0x0064 0x02F0 0x05A4 0x0 0x0
+#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2                       0x0064 0x02F0 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR                        0x0064 0x02F0 0x0000 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M                   0x0064 0x02F0 0x0000 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP                           0x0064 0x02F0 0x066C 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                          0x0064 0x02F0 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00                    0x0064 0x02F0 0x0610 0x6 0x1
+#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET                    0x0064 0x02F0 0x0000 0x7 0x0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX                        0x0064 0x02F0 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX                        0x0064 0x02F0 0x0624 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA                            0x0068 0x02F4 0x05A8 0x0 0x1
+#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3                       0x0068 0x02F4 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC                         0x0068 0x02F4 0x0660 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO03__REF_CLK_32K                         0x0068 0x02F4 0x0000 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B                         0x0068 0x02F4 0x0668 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                          0x0068 0x02F4 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK                     0x0068 0x02F4 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK                      0x0068 0x02F4 0x0000 0x7 0x0
+#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX                        0x0068 0x02F4 0x0624 0x8 0x1
+#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX                        0x0068 0x02F4 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1                      0x006C 0x02F8 0x0574 0x0 0x1
+#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT                            0x006C 0x02F8 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR                        0x006C 0x02F8 0x0000 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M                         0x006C 0x02F8 0x0000 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B                      0x006C 0x02F8 0x0000 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                          0x006C 0x02F8 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN                0x006C 0x02F8 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX                        0x006C 0x02F8 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX                        0x006C 0x02F8 0x0644 0x8 0x2
+#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2                      0x0070 0x02FC 0x057C 0x0 0x1
+#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT                            0x0070 0x02FC 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID                      0x0070 0x02FC 0x04BC 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD                           0x0070 0x02FC 0x0530 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT                      0x0070 0x02FC 0x0000 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05                          0x0070 0x02FC 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT               0x0070 0x02FC 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX                        0x0070 0x02FC 0x0644 0x8 0x3
+#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX                        0x0070 0x02FC 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO                          0x0074 0x0300 0x0578 0x0 0x0
+#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO                          0x0074 0x0300 0x0580 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE                    0x0074 0x0300 0x0000 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK                            0x0074 0x0300 0x0000 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP                           0x0074 0x0300 0x069C 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06                          0x0074 0x0300 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT                            0x0074 0x0300 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B                        0x0074 0x0300 0x0000 0x7 0x0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS                       0x0074 0x0300 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS                       0x0074 0x0300 0x0620 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC                           0x0078 0x0304 0x0000 0x0 0x0
+#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC                           0x0078 0x0304 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE                   0x0078 0x0304 0x0000 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK                          0x0078 0x0304 0x0528 0x3 0x0
+#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B                         0x0078 0x0304 0x0674 0x4 0x1
+#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07                          0x0078 0x0304 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO07__CCM_STOP                            0x0078 0x0304 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS                       0x0078 0x0304 0x0620 0x8 0x1
+#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS                       0x0078 0x0304 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT                            0x007C 0x0308 0x0000 0x0 0x0
+#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B                        0x007C 0x0308 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT                           0x007C 0x0308 0x0000 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC                           0x007C 0x0308 0x052C 0x3 0x1
+#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT                      0x007C 0x0308 0x0000 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08                          0x007C 0x0308 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY                        0x007C 0x0308 0x04C0 0x6 0x1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS                       0x007C 0x0308 0x0640 0x8 0x1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS                       0x007C 0x0308 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT                            0x0080 0x030C 0x0000 0x0 0x0
+#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY                      0x0080 0x030C 0x0000 0x1 0x0
+#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN                            0x0080 0x030C 0x0618 0x2 0x0
+#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC                           0x0080 0x030C 0x0524 0x3 0x1
+#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B                      0x0080 0x030C 0x0000 0x4 0x0
+#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09                          0x0080 0x030C 0x0000 0x5 0x0
+#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B                      0x0080 0x030C 0x0000 0x6 0x0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS                       0x0080 0x030C 0x0000 0x8 0x0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS                       0x0080 0x030C 0x0640 0x8 0x2
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX                     0x0084 0x0310 0x0000 0x0 0x0
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX                     0x0084 0x0310 0x0624 0x0 0x2
+#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02                    0x0084 0x0310 0x0000 0x1 0x0
+#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL                         0x0084 0x0310 0x05B4 0x2 0x0
+#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02                       0x0084 0x0310 0x04C4 0x3 0x1
+#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1                    0x0084 0x0310 0x0000 0x4 0x0
+#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16                       0x0084 0x0310 0x0000 0x5 0x0
+#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT                        0x0084 0x0310 0x0000 0x8 0x0
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX                     0x0088 0x0314 0x0624 0x0 0x3
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX                     0x0088 0x0314 0x0000 0x0 0x0
+#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03                    0x0088 0x0314 0x0000 0x1 0x0
+#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA                         0x0088 0x0314 0x05B8 0x2 0x0
+#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03                       0x0088 0x0314 0x04C8 0x3 0x1
+#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK                         0x0088 0x0314 0x0594 0x4 0x0
+#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17                       0x0088 0x0314 0x0000 0x5 0x0
+#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN                         0x0088 0x0314 0x0618 0x8 0x1
+#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS                      0x008C 0x0318 0x0000 0x0 0x0
+#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS                      0x008C 0x0318 0x0620 0x0 0x2
+#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK                       0x008C 0x0318 0x0000 0x1 0x0
+#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP                          0x008C 0x0318 0x066C 0x2 0x1
+#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04                         0x008C 0x0318 0x04D8 0x3 0x0
+#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN               0x008C 0x0318 0x0000 0x4 0x0
+#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18                         0x008C 0x0318 0x0000 0x5 0x0
+#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP                          0x008C 0x0318 0x069C 0x8 0x1
+#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS                      0x0090 0x031C 0x0620 0x0 0x3
+#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS                      0x0090 0x031C 0x0000 0x0 0x0
+#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER                        0x0090 0x031C 0x0000 0x1 0x0
+#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B                        0x0090 0x031C 0x0668 0x2 0x1
+#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05                         0x0090 0x031C 0x04CC 0x3 0x1
+#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT              0x0090 0x031C 0x0000 0x4 0x0
+#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19                         0x0090 0x031C 0x0000 0x5 0x0
+#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B                        0x0090 0x031C 0x0674 0x8 0x2
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX                     0x0094 0x0320 0x0000 0x0 0x0
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX                     0x0094 0x0320 0x062C 0x0 0x0
+#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02                    0x0094 0x0320 0x0000 0x1 0x0
+#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL                         0x0094 0x0320 0x05BC 0x2 0x0
+#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06                       0x0094 0x0320 0x04DC 0x3 0x0
+#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1                    0x0094 0x0320 0x058C 0x4 0x1
+#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20                       0x0094 0x0320 0x0000 0x5 0x0
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0                       0x0094 0x0320 0x0560 0x8 0x0
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX                     0x0098 0x0324 0x062C 0x0 0x1
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX                     0x0098 0x0324 0x0000 0x0 0x0
+#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03                    0x0098 0x0324 0x0000 0x1 0x0
+#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA                         0x0098 0x0324 0x05C0 0x2 0x0
+#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07                       0x0098 0x0324 0x04E0 0x3 0x0
+#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2                    0x0098 0x0324 0x0590 0x4 0x0
+#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21                       0x0098 0x0324 0x0000 0x5 0x0
+#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE                         0x0098 0x0324 0x0000 0x7 0x0
+#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK                      0x0098 0x0324 0x0554 0x8 0x0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS                      0x009C 0x0328 0x0000 0x0 0x0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS                      0x009C 0x0328 0x0628 0x0 0x0
+#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS                          0x009C 0x0328 0x0000 0x1 0x0
+#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX                        0x009C 0x0328 0x0000 0x2 0x0
+#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08                         0x009C 0x0328 0x04E4 0x3 0x0
+#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2                      0x009C 0x0328 0x0000 0x4 0x0
+#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22                         0x009C 0x0328 0x0000 0x5 0x0
+#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B                           0x009C 0x0328 0x0000 0x7 0x0
+#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI                        0x009C 0x0328 0x055C 0x8 0x0
+#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS                      0x00A0 0x032C 0x0628 0x0 0x1
+#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS                      0x00A0 0x032C 0x0000 0x0 0x0
+#define MX6UL_PAD_UART2_RTS_B__ENET1_COL                          0x00A0 0x032C 0x0000 0x1 0x0
+#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX                        0x00A0 0x032C 0x0588 0x2 0x0
+#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09                         0x00A0 0x032C 0x04E8 0x3 0x0
+#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3                      0x00A0 0x032C 0x0000 0x4 0x0
+#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23                         0x00A0 0x032C 0x0000 0x5 0x0
+#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL                           0x00A0 0x032C 0x0000 0x7 0x0
+#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO                        0x00A0 0x032C 0x0558 0x8 0x0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX                     0x00A4 0x0330 0x0000 0x0 0x0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX                     0x00A4 0x0330 0x0634 0x0 0x0
+#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02                    0x00A4 0x0330 0x0000 0x1 0x0
+#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD                    0x00A4 0x0330 0x0000 0x2 0x0
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01                       0x00A4 0x0330 0x04D4 0x3 0x0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS                    0x00A4 0x0330 0x0000 0x4 0x0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS                    0x00A4 0x0330 0x0628 0x4 0x2
+#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24                       0x00A4 0x0330 0x0000 0x5 0x0
+#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT                     0x00A4 0x0330 0x0000 0x7 0x0
+#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID                   0x00A4 0x0330 0x04B8 0x8 0x1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX                     0x00A8 0x0334 0x0634 0x0 0x1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX                     0x00A8 0x0334 0x0000 0x0 0x0
+#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03                    0x00A8 0x0334 0x0000 0x1 0x0
+#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD                    0x00A8 0x0334 0x0000 0x2 0x0
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00                       0x00A8 0x0334 0x04D0 0x3 0x0
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS                    0x00A8 0x0334 0x0628 0x4 0x3
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS                    0x00A8 0x0334 0x0000 0x4 0x0
+#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25                       0x00A8 0x0334 0x0000 0x5 0x0
+#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT                        0x00A8 0x0334 0x0000 0x8 0x0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS                      0x00AC 0x0338 0x0000 0x0 0x0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS                      0x00AC 0x0338 0x0630 0x0 0x0
+#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK                       0x00AC 0x0338 0x0000 0x1 0x0
+#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX                        0x00AC 0x0338 0x0000 0x2 0x0
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10                         0x00AC 0x0338 0x04EC 0x3 0x0
+#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN               0x00AC 0x0338 0x0000 0x4 0x0
+#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26                         0x00AC 0x0338 0x0000 0x5 0x0
+#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT                          0x00AC 0x0338 0x0000 0x8 0x0
+#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS                      0x00B0 0x033C 0x0630 0x0 0x1
+#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS                      0x00B0 0x033C 0x0000 0x0 0x0
+#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER                        0x00B0 0x033C 0x0000 0x1 0x0
+#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX                        0x00B0 0x033C 0x0584 0x2 0x0
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11                         0x00B0 0x033C 0x04F0 0x3 0x0
+#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT              0x00B0 0x033C 0x0000 0x4 0x0
+#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27                         0x00B0 0x033C 0x0000 0x5 0x0
+#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B                       0x00B0 0x033C 0x0000 0x8 0x0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX                     0x00B4 0x0340 0x0000 0x0 0x0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX                     0x00B4 0x0340 0x063C 0x0 0x0
+#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02                    0x00B4 0x0340 0x0000 0x1 0x0
+#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL                         0x00B4 0x0340 0x05A4 0x2 0x1
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12                       0x00B4 0x0340 0x04F4 0x3 0x0
+#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02              0x00B4 0x0340 0x0000 0x4 0x0
+#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28                       0x00B4 0x0340 0x0000 0x5 0x0
+#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK                      0x00B4 0x0340 0x0544 0x8 0x1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX                     0x00B8 0x0344 0x063C 0x0 0x1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX                     0x00B8 0x0344 0x0000 0x0 0x0
+#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03                    0x00B8 0x0344 0x0000 0x1 0x0
+#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA                         0x00B8 0x0344 0x05A8 0x2 0x2
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13                       0x00B8 0x0344 0x04F8 0x3 0x0
+#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01              0x00B8 0x0344 0x0000 0x4 0x0
+#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29                       0x00B8 0x0344 0x0000 0x5 0x0
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0                       0x00B8 0x0344 0x0550 0x8 0x1
+#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30                       0x00BC 0x0348 0x0000 0x5 0x0
+#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI                      0x00BC 0x0348 0x054C 0x8 0x0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX                     0x00BC 0x0348 0x0000 0x0 0x0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX                     0x00BC 0x0348 0x0644 0x0 0x4
+#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS                        0x00BC 0x0348 0x0000 0x1 0x0
+#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL                         0x00BC 0x0348 0x05AC 0x2 0x2
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14                       0x00BC 0x0348 0x04FC 0x3 0x0
+#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00              0x00BC 0x0348 0x0000 0x4 0x0
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX                     0x00C0 0x034C 0x0644 0x0 0x5
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX                     0x00C0 0x034C 0x0000 0x0 0x0
+#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL                        0x00C0 0x034C 0x0000 0x1 0x0
+#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA                         0x00C0 0x034C 0x05B0 0x2 0x2
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15                       0x00C0 0x034C 0x0500 0x3 0x0
+#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB                  0x00C0 0x034C 0x0000 0x4 0x0
+#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31                       0x00C0 0x034C 0x0000 0x5 0x0
+#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO                      0x00C0 0x034C 0x0548 0x8 0x1
+#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00                   0x00C4 0x0350 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS                   0x00C4 0x0350 0x0638 0x1 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS                   0x00C4 0x0350 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT                        0x00C4 0x0350 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16                      0x00C4 0x0350 0x0504 0x3 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX                     0x00C4 0x0350 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00                      0x00C4 0x0350 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00                       0x00C4 0x0350 0x05D0 0x6 0x0
+#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL                     0x00C4 0x0350 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01                   0x00C8 0x0354 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS                   0x00C8 0x0354 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS                   0x00C8 0x0354 0x0638 0x1 0x1
+#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT                        0x00C8 0x0354 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17                      0x00C8 0x0354 0x0508 0x3 0x0
+#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX                     0x00C8 0x0354 0x0584 0x4 0x1
+#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01                      0x00C8 0x0354 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00                       0x00C8 0x0354 0x05C4 0x6 0x0
+#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL                     0x00C8 0x0354 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN                        0x00CC 0x0358 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS                      0x00CC 0x0358 0x0640 0x1 0x3
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS                      0x00CC 0x0358 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_RX_EN__REF_CLK_32K                        0x00CC 0x0358 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18                         0x00CC 0x0358 0x050C 0x3 0x0
+#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX                        0x00CC 0x0358 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02                         0x00CC 0x0358 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01                          0x00CC 0x0358 0x05D4 0x6 0x0
+#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT                     0x00CC 0x0358 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00                   0x00D0 0x035C 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS                   0x00D0 0x035C 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                   0x00D0 0x035C 0x0640 0x1 0x4
+#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M                     0x00D0 0x035C 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19                      0x00D0 0x035C 0x0510 0x3 0x0
+#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX                     0x00D0 0x035C 0x0588 0x4 0x1
+#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03                      0x00D0 0x035C 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01                       0x00D0 0x035C 0x05C8 0x6 0x0
+#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT                  0x00D0 0x035C 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01                   0x00D4 0x0360 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS                   0x00D4 0x0360 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS                   0x00D4 0x0360 0x0648 0x1 0x2
+#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT                        0x00D4 0x0360 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20                      0x00D4 0x0360 0x0514 0x3 0x0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO                      0x00D4 0x0360 0x0580 0x4 0x1
+#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04                      0x00D4 0x0360 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02                       0x00D4 0x0360 0x05D8 0x6 0x0
+#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB            0x00D4 0x0360 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN                        0x00D8 0x0364 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS                      0x00D8 0x0364 0x0648 0x1 0x3
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS                      0x00D8 0x0364 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT                           0x00D8 0x0364 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21                         0x00D8 0x0364 0x0518 0x3 0x0
+#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC                          0x00D8 0x0364 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05                         0x00D8 0x0364 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02                          0x00D8 0x0364 0x05CC 0x6 0x0
+#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB               0x00D8 0x0364 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK                      0x00DC 0x0368 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS                     0x00DC 0x0368 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS                     0x00DC 0x0368 0x0650 0x1 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT                          0x00DC 0x0368 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22                        0x00DC 0x0368 0x051C 0x3 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                    0x00DC 0x0368 0x0574 0x4 0x2
+#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06                        0x00DC 0x0368 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03                         0x00DC 0x0368 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK                          0x00DC 0x0368 0x0594 0x8 0x1
+#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER                        0x00E0 0x036C 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS                      0x00E0 0x036C 0x0650 0x1 0x1
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS                      0x00E0 0x036C 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT                           0x00E0 0x036C 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23                         0x00E0 0x036C 0x0520 0x3 0x0
+#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE                            0x00E0 0x036C 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07                         0x00E0 0x036C 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03                          0x00E0 0x036C 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2                      0x00E0 0x036C 0x0590 0x8 0x1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00                   0x00E4 0x0370 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX                    0x00E4 0x0370 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX                    0x00E4 0x0370 0x064C 0x1 0x1
+#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD                 0x00E4 0x0370 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL                        0x00E4 0x0370 0x05B4 0x3 0x1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO                      0x00E4 0x0370 0x0578 0x4 0x1
+#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08                      0x00E4 0x0370 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04                       0x00E4 0x0370 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR                    0x00E4 0x0370 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01                   0x00E8 0x0374 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX                    0x00E8 0x0374 0x064C 0x1 0x2
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX                    0x00E8 0x0374 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK                  0x00E8 0x0374 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA                        0x00E8 0x0374 0x05B8 0x3 0x1
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC                       0x00E8 0x0374 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09                      0x00E8 0x0374 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04                       0x00E8 0x0374 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC                     0x00E8 0x0374 0x0664 0x8 0x1
+#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN                        0x00EC 0x0378 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX                       0x00EC 0x0378 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX                       0x00EC 0x0378 0x0654 0x1 0x0
+#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B                   0x00EC 0x0378 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL                           0x00EC 0x0378 0x05BC 0x3 0x1
+#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26                         0x00EC 0x0378 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10                         0x00EC 0x0378 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05                          0x00EC 0x0378 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M                  0x00EC 0x0378 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00                   0x00F0 0x037C 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX                    0x00F0 0x037C 0x0654 0x1 0x1
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX                    0x00F0 0x037C 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN                 0x00F0 0x037C 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA                        0x00F0 0x037C 0x05C0 0x3 0x1
+#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02                      0x00F0 0x037C 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11                      0x00F0 0x037C 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05                       0x00F0 0x037C 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M                     0x00F0 0x037C 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01                   0x00F4 0x0380 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX                    0x00F4 0x0380 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX                    0x00F4 0x0380 0x065C 0x1 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD                 0x00F4 0x0380 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK                     0x00F4 0x0380 0x0564 0x3 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03                      0x00F4 0x0380 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12                      0x00F4 0x0380 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06                       0x00F4 0x0380 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR                    0x00F4 0x0380 0x0000 0x8 0x0
+#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN                        0x00F8 0x0384 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX                       0x00F8 0x0384 0x065C 0x1 0x1
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX                       0x00F8 0x0384 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK                     0x00F8 0x0384 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI                        0x00F8 0x0384 0x056C 0x3 0x0
+#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN                   0x00F8 0x0384 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13                         0x00F8 0x0384 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06                          0x00F8 0x0384 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC                        0x00F8 0x0384 0x0660 0x8 0x1
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK                      0x00FC 0x0388 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS                     0x00FC 0x0388 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS                     0x00FC 0x0388 0x0658 0x1 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B                  0x00FC 0x0388 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO                       0x00FC 0x0388 0x0568 0x3 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                    0x00FC 0x0388 0x057C 0x4 0x2
+#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14                        0x00FC 0x0388 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07                         0x00FC 0x0388 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID                    0x00FC 0x0388 0x04BC 0x8 0x1
+#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER                        0x0100 0x038C 0x0000 0x0 0x0
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS                      0x0100 0x038C 0x0658 0x1 0x1
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS                      0x0100 0x038C 0x0000 0x1 0x0
+#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN                    0x0100 0x038C 0x0000 0x2 0x0
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0                         0x0100 0x038C 0x0570 0x3 0x0
+#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25                         0x0100 0x038C 0x0000 0x4 0x0
+#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15                         0x0100 0x038C 0x0000 0x5 0x0
+#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07                          0x0100 0x038C 0x0000 0x6 0x0
+#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY                     0x0100 0x038C 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_CLK__LCDIF_CLK                              0x0104 0x0390 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN                           0x0104 0x0390 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX                           0x0104 0x0390 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX                           0x0104 0x0390 0x063C 0x2 0x2
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK                              0x0104 0x0390 0x0600 0x3 0x0
+#define MX6UL_PAD_LCD_CLK__EIM_CS2_B                              0x0104 0x0390 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_CLK__GPIO3_IO00                             0x0104 0x0390 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                   0x0104 0x0390 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE                        0x0108 0x0394 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E                          0x0108 0x0394 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX                        0x0108 0x0394 0x063C 0x2 0x3
+#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX                        0x0108 0x0394 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC                        0x0108 0x0394 0x060C 0x3 0x0
+#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B                           0x0108 0x0394 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01                          0x0108 0x0394 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY                          0x0108 0x0394 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC                          0x010C 0x0398 0x05DC 0x0 0x0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS                             0x010C 0x0398 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS                        0x010C 0x0398 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS                        0x010C 0x0398 0x0638 0x2 0x2
+#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK                         0x010C 0x0398 0x0608 0x3 0x0
+#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB                 0x010C 0x0398 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02                           0x010C 0x0398 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1                           0x010C 0x0398 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC                          0x0110 0x039C 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY                           0x0110 0x039C 0x05DC 0x1 0x1
+#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS                        0x0110 0x039C 0x0638 0x2 0x3
+#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS                        0x0110 0x039C 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA                         0x0110 0x039C 0x0604 0x3 0x0
+#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B                         0x0110 0x039C 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03                           0x0110 0x039C 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2                           0x0110 0x039C 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_RESET__LCDIF_RESET                          0x0114 0x03A0 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_RESET__LCDIF_CS                             0x0114 0x03A0 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI                     0x0114 0x03A0 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA                         0x0114 0x03A0 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY                       0x0114 0x03A0 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_RESET__GPIO3_IO04                           0x0114 0x03A0 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3                           0x0114 0x03A0 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00                        0x0118 0x03A4 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA00__PWM1_OUT                            0x0118 0x03A4 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0                    0x0118 0x03A4 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN                0x0118 0x03A4 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA00__I2C3_SDA                            0x0118 0x03A4 0x05B8 0x4 0x2
+#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05                          0x0118 0x03A4 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00                        0x0118 0x03A4 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK                           0x0118 0x03A4 0x05E0 0x8 0x1
+#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01                        0x011C 0x03A8 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA01__PWM2_OUT                            0x011C 0x03A8 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1                    0x011C 0x03A8 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT               0x011C 0x03A8 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA01__I2C3_SCL                            0x011C 0x03A8 0x05B4 0x4 0x2
+#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06                          0x011C 0x03A8 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01                        0x011C 0x03A8 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC                        0x011C 0x03A8 0x05EC 0x8 0x0
+#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02                        0x0120 0x03AC 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA02__PWM3_OUT                            0x0120 0x03AC 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2                    0x0120 0x03AC 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN                0x0120 0x03AC 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA02__I2C4_SDA                            0x0120 0x03AC 0x05C0 0x4 0x2
+#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07                          0x0120 0x03AC 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02                        0x0120 0x03AC 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK                        0x0120 0x03AC 0x05E8 0x8 0x0
+#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03                        0x0124 0x03B0 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA03__PWM4_OUT                            0x0124 0x03B0 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3                    0x0124 0x03B0 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT               0x0124 0x03B0 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA03__I2C4_SCL                            0x0124 0x03B0 0x05BC 0x4 0x2
+#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08                          0x0124 0x03B0 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03                        0x0124 0x03B0 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA                        0x0124 0x03B0 0x05E4 0x8 0x0
+#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04                        0x0128 0x03B4 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS                       0x0128 0x03B4 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS                       0x0128 0x03B4 0x0658 0x1 0x2
+#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4                    0x0128 0x03B4 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN                0x0128 0x03B4 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK                        0x0128 0x03B4 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09                          0x0128 0x03B4 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04                        0x0128 0x03B4 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA                        0x0128 0x03B4 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05                        0x012C 0x03B8 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS                       0x012C 0x03B8 0x0658 0x1 0x3
+#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS                       0x012C 0x03B8 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5                    0x012C 0x03B8 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT               0x012C 0x03B8 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT                           0x012C 0x03B8 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10                          0x012C 0x03B8 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05                        0x012C 0x03B8 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1                          0x012C 0x03B8 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06                        0x0130 0x03BC 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS                       0x0130 0x03BC 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS                       0x0130 0x03BC 0x0650 0x1 0x2
+#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6                    0x0130 0x03BC 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN                0x0130 0x03BC 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK                          0x0130 0x03BC 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11                          0x0130 0x03BC 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06                        0x0130 0x03BC 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2                          0x0130 0x03BC 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07                        0x0134 0x03C0 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS                       0x0134 0x03C0 0x0650 0x1 0x3
+#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS                       0x0134 0x03C0 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7                    0x0134 0x03C0 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT               0x0134 0x03C0 0x0000 0x3 0x0
+#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK                       0x0134 0x03C0 0x061C 0x4 0x0
+#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12                          0x0134 0x03C0 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07                        0x0134 0x03C0 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3                          0x0134 0x03C0 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08                        0x0138 0x03C4 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA08__SPDIF_IN                            0x0138 0x03C4 0x0618 0x1 0x2
+#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8                    0x0138 0x03C4 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16                          0x0138 0x03C4 0x0504 0x3 0x1
+#define MX6UL_PAD_LCD_DATA08__EIM_DATA00                          0x0138 0x03C4 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13                          0x0138 0x03C4 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08                        0x0138 0x03C4 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX                         0x0138 0x03C4 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09                        0x013C 0x03C8 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK                           0x013C 0x03C8 0x0600 0x1 0x1
+#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9                    0x013C 0x03C8 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17                          0x013C 0x03C8 0x0508 0x3 0x1
+#define MX6UL_PAD_LCD_DATA09__EIM_DATA01                          0x013C 0x03C8 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14                          0x013C 0x03C8 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09                        0x013C 0x03C8 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX                         0x013C 0x03C8 0x0584 0x8 0x2
+#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10                        0x0140 0x03CC 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC                        0x0140 0x03CC 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10                   0x0140 0x03CC 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18                          0x0140 0x03CC 0x050C 0x3 0x1
+#define MX6UL_PAD_LCD_DATA10__EIM_DATA02                          0x0140 0x03CC 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15                          0x0140 0x03CC 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10                        0x0140 0x03CC 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX                         0x0140 0x03CC 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11                        0x0144 0x03D0 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK                        0x0144 0x03D0 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11                   0x0144 0x03D0 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19                          0x0144 0x03D0 0x0510 0x3 0x1
+#define MX6UL_PAD_LCD_DATA11__EIM_DATA03                          0x0144 0x03D0 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16                          0x0144 0x03D0 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11                        0x0144 0x03D0 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX                         0x0144 0x03D0 0x0588 0x8 0x2
+#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12                        0x0148 0x03D4 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC                        0x0148 0x03D4 0x060C 0x1 0x1
+#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12                   0x0148 0x03D4 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20                          0x0148 0x03D4 0x0514 0x3 0x1
+#define MX6UL_PAD_LCD_DATA12__EIM_DATA04                          0x0148 0x03D4 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17                          0x0148 0x03D4 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12                        0x0148 0x03D4 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY                          0x0148 0x03D4 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13                        0x014C 0x03D8 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK                        0x014C 0x03D8 0x0608 0x1 0x1
+#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13                   0x014C 0x03D8 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21                          0x014C 0x03D8 0x0518 0x3 0x1
+#define MX6UL_PAD_LCD_DATA13__EIM_DATA05                          0x014C 0x03D8 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18                          0x014C 0x03D8 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13                        0x014C 0x03D8 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B                      0x014C 0x03D8 0x0000 0x8 0x0
+#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14                        0x0150 0x03DC 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA                        0x0150 0x03DC 0x0604 0x1 0x1
+#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14                   0x0150 0x03DC 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22                          0x0150 0x03DC 0x051C 0x3 0x1
+#define MX6UL_PAD_LCD_DATA14__EIM_DATA06                          0x0150 0x03DC 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19                          0x0150 0x03DC 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14                        0x0150 0x03DC 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4                        0x0150 0x03DC 0x068C 0x8 0x0
+#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15                        0x0154 0x03E0 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA                        0x0154 0x03E0 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15                   0x0154 0x03E0 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23                          0x0154 0x03E0 0x0520 0x3 0x1
+#define MX6UL_PAD_LCD_DATA15__EIM_DATA07                          0x0154 0x03E0 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20                          0x0154 0x03E0 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15                        0x0154 0x03E0 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5                        0x0154 0x03E0 0x0690 0x8 0x0
+#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16                        0x0158 0x03E4 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX                        0x0158 0x03E4 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX                        0x0158 0x03E4 0x0654 0x1 0x2
+#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK                 0x0158 0x03E4 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01                          0x0158 0x03E4 0x04D4 0x3 0x1
+#define MX6UL_PAD_LCD_DATA16__EIM_DATA08                          0x0158 0x03E4 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21                          0x0158 0x03E4 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24                        0x0158 0x03E4 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6                        0x0158 0x03E4 0x0694 0x8 0x0
+#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17                        0x015C 0x03E8 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX                        0x015C 0x03E8 0x0654 0x1 0x3
+#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX                        0x015C 0x03E8 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL                 0x015C 0x03E8 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00                          0x015C 0x03E8 0x04D0 0x3 0x1
+#define MX6UL_PAD_LCD_DATA17__EIM_DATA09                          0x015C 0x03E8 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22                          0x015C 0x03E8 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25                        0x015C 0x03E8 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7                        0x015C 0x03E8 0x0698 0x8 0x0
+#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18                        0x0160 0x03EC 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA18__PWM5_OUT                            0x0160 0x03EC 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO                    0x0160 0x03EC 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10                          0x0160 0x03EC 0x04EC 0x3 0x1
+#define MX6UL_PAD_LCD_DATA18__EIM_DATA10                          0x0160 0x03EC 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23                          0x0160 0x03EC 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26                        0x0160 0x03EC 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD                          0x0160 0x03EC 0x0678 0x8 0x1
+#define MX6UL_PAD_LCD_DATA19__EIM_DATA11                          0x0164 0x03F0 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24                          0x0164 0x03F0 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27                        0x0164 0x03F0 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK                          0x0164 0x03F0 0x0670 0x8 0x1
+#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19                        0x0164 0x03F0 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA19__PWM6_OUT                            0x0164 0x03F0 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY                      0x0164 0x03F0 0x0000 0x2 0x0
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11                          0x0164 0x03F0 0x04F0 0x3 0x1
+#define MX6UL_PAD_LCD_DATA20__EIM_DATA12                          0x0168 0x03F4 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25                          0x0168 0x03F4 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28                        0x0168 0x03F4 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0                        0x0168 0x03F4 0x067C 0x8 0x1
+#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20                        0x0168 0x03F4 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX                        0x0168 0x03F4 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX                        0x0168 0x03F4 0x065C 0x1 0x2
+#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK                         0x0168 0x03F4 0x0534 0x2 0x0
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12                          0x0168 0x03F4 0x04F4 0x3 0x1
+#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21                        0x016C 0x03F8 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX                        0x016C 0x03F8 0x065C 0x1 0x3
+#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX                        0x016C 0x03F8 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0                          0x016C 0x03F8 0x0540 0x2 0x0
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13                          0x016C 0x03F8 0x04F8 0x3 0x1
+#define MX6UL_PAD_LCD_DATA21__EIM_DATA13                          0x016C 0x03F8 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26                          0x016C 0x03F8 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29                        0x016C 0x03F8 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1                        0x016C 0x03F8 0x0680 0x8 0x1
+#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22                        0x0170 0x03FC 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT                           0x0170 0x03FC 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI                         0x0170 0x03FC 0x053C 0x2 0x0
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14                          0x0170 0x03FC 0x04FC 0x3 0x1
+#define MX6UL_PAD_LCD_DATA22__EIM_DATA14                          0x0170 0x03FC 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27                          0x0170 0x03FC 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30                        0x0170 0x03FC 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2                        0x0170 0x03FC 0x0684 0x8 0x0
+#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23                        0x0174 0x0400 0x0000 0x0 0x0
+#define MX6UL_PAD_LCD_DATA23__MQS_LEFT                            0x0174 0x0400 0x0000 0x1 0x0
+#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO                         0x0174 0x0400 0x0538 0x2 0x0
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15                          0x0174 0x0400 0x0500 0x3 0x1
+#define MX6UL_PAD_LCD_DATA23__EIM_DATA15                          0x0174 0x0400 0x0000 0x4 0x0
+#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28                          0x0174 0x0400 0x0000 0x5 0x0
+#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31                        0x0174 0x0400 0x0000 0x6 0x0
+#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3                        0x0174 0x0400 0x0688 0x8 0x1
+#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B                         0x0178 0x0404 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK                           0x0178 0x0404 0x0670 0x1 0x2
+#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK                          0x0178 0x0404 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00                            0x0178 0x0404 0x05D0 0x3 0x1
+#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00                           0x0178 0x0404 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00                           0x0178 0x0404 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2                           0x0178 0x0404 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B                         0x017C 0x0408 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD                           0x017C 0x0408 0x0678 0x1 0x2
+#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B                         0x017C 0x0408 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00                            0x017C 0x0408 0x05C4 0x3 0x1
+#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01                           0x017C 0x0408 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01                           0x017C 0x0408 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3                           0x017C 0x0408 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00                     0x0180 0x040C 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0                       0x0180 0x040C 0x067C 0x1 0x2
+#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B                       0x0180 0x040C 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01                          0x0180 0x040C 0x05D4 0x3 0x1
+#define MX6UL_PAD_NAND_DATA00__EIM_AD08                           0x0180 0x040C 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02                         0x0180 0x040C 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY                         0x0180 0x040C 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01                     0x0184 0x0410 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1                       0x0184 0x0410 0x0680 0x1 0x2
+#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS                         0x0184 0x0410 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01                          0x0184 0x0410 0x05C8 0x3 0x1
+#define MX6UL_PAD_NAND_DATA01__EIM_AD09                           0x0184 0x0410 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03                         0x0184 0x0410 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1                         0x0184 0x0410 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02                     0x0188 0x0414 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2                       0x0188 0x0414 0x0684 0x1 0x1
+#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00                      0x0188 0x0414 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02                          0x0188 0x0414 0x05D8 0x3 0x1
+#define MX6UL_PAD_NAND_DATA02__EIM_AD10                           0x0188 0x0414 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04                         0x0188 0x0414 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2                         0x0188 0x0414 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03                     0x018C 0x0418 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3                       0x018C 0x0418 0x0688 0x1 0x2
+#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01                      0x018C 0x0418 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02                          0x018C 0x0418 0x05CC 0x3 0x1
+#define MX6UL_PAD_NAND_DATA03__EIM_AD11                           0x018C 0x0418 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05                         0x018C 0x0418 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3                         0x018C 0x0418 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04                     0x0190 0x041C 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4                       0x0190 0x041C 0x068C 0x1 0x1
+#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02                      0x0190 0x041C 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK                        0x0190 0x041C 0x0564 0x3 0x1
+#define MX6UL_PAD_NAND_DATA04__EIM_AD12                           0x0190 0x041C 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06                         0x0190 0x041C 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX                       0x0190 0x041C 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX                       0x0190 0x041C 0x062C 0x8 0x2
+#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05                     0x0194 0x0420 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5                       0x0194 0x0420 0x0690 0x1 0x1
+#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03                      0x0194 0x0420 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI                        0x0194 0x0420 0x056C 0x3 0x1
+#define MX6UL_PAD_NAND_DATA05__EIM_AD13                           0x0194 0x0420 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07                         0x0194 0x0420 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX                       0x0194 0x0420 0x062C 0x8 0x3
+#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX                       0x0194 0x0420 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06                     0x0198 0x0424 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6                       0x0198 0x0424 0x0694 0x1 0x1
+#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK                       0x0198 0x0424 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO                        0x0198 0x0424 0x0568 0x3 0x1
+#define MX6UL_PAD_NAND_DATA06__EIM_AD14                           0x0198 0x0424 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08                         0x0198 0x0424 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS                      0x0198 0x0424 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS                      0x0198 0x0424 0x0628 0x8 0x4
+#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07                     0x019C 0x0428 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7                       0x019C 0x0428 0x0698 0x1 0x1
+#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B                       0x019C 0x0428 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0                         0x019C 0x0428 0x0570 0x3 0x1
+#define MX6UL_PAD_NAND_DATA07__EIM_AD15                           0x019C 0x0428 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09                         0x019C 0x0428 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS                      0x019C 0x0428 0x0628 0x8 0x5
+#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS                      0x019C 0x0428 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE                           0x01A0 0x042C 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B                        0x01A0 0x042C 0x0000 0x1 0x0
+#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS                            0x01A0 0x042C 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_ALE__PWM3_OUT                              0x01A0 0x042C 0x0000 0x3 0x0
+#define MX6UL_PAD_NAND_ALE__EIM_ADDR17                            0x01A0 0x042C 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_ALE__GPIO4_IO10                            0x01A0 0x042C 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1                            0x01A0 0x042C 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B                         0x01A4 0x0430 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B                       0x01A4 0x0430 0x0000 0x1 0x0
+#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK                          0x01A4 0x0430 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_WP_B__PWM4_OUT                             0x01A4 0x0430 0x0000 0x3 0x0
+#define MX6UL_PAD_NAND_WP_B__EIM_BCLK                             0x01A4 0x0430 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11                           0x01A4 0x0430 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY                           0x01A4 0x0430 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B                   0x01A8 0x0434 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4                      0x01A8 0x0434 0x0000 0x1 0x0
+#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00                     0x01A8 0x0434 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0                        0x01A8 0x0434 0x0560 0x3 0x1
+#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B                         0x01A8 0x0434 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12                        0x01A8 0x0434 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX                      0x01A8 0x0434 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX                      0x01A8 0x0434 0x0634 0x8 0x2
+#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B                       0x01AC 0x0438 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5                        0x01AC 0x0438 0x0000 0x1 0x0
+#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01                       0x01AC 0x0438 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK                         0x01AC 0x0438 0x0554 0x3 0x1
+#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B                         0x01AC 0x0438 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13                          0x01AC 0x0438 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX                        0x01AC 0x0438 0x0634 0x8 0x3
+#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX                        0x01AC 0x0438 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B                       0x01B0 0x043C 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6                        0x01B0 0x043C 0x0000 0x1 0x0
+#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02                       0x01B0 0x043C 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI                         0x01B0 0x043C 0x055C 0x3 0x1
+#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18                          0x01B0 0x043C 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14                          0x01B0 0x043C 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS                       0x01B0 0x043C 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS                       0x01B0 0x043C 0x0630 0x8 0x2
+#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE                           0x01B4 0x0440 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7                          0x01B4 0x0440 0x0000 0x1 0x0
+#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03                         0x01B4 0x0440 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO                           0x01B4 0x0440 0x0558 0x3 0x1
+#define MX6UL_PAD_NAND_CLE__EIM_ADDR16                            0x01B4 0x0440 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_CLE__GPIO4_IO15                            0x01B4 0x0440 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS                         0x01B4 0x0440 0x0630 0x8 0x3
+#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS                         0x01B4 0x0440 0x0000 0x8 0x0
+#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS                           0x01B8 0x0444 0x0000 0x0 0x0
+#define MX6UL_PAD_NAND_DQS__CSI_FIELD                             0x01B8 0x0444 0x0530 0x1 0x1
+#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B                          0x01B8 0x0444 0x0000 0x2 0x0
+#define MX6UL_PAD_NAND_DQS__PWM5_OUT                              0x01B8 0x0444 0x0000 0x3 0x0
+#define MX6UL_PAD_NAND_DQS__EIM_WAIT                              0x01B8 0x0444 0x0000 0x4 0x0
+#define MX6UL_PAD_NAND_DQS__GPIO4_IO16                            0x01B8 0x0444 0x0000 0x5 0x0
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01                      0x01B8 0x0444 0x0614 0x6 0x1
+#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK                         0x01B8 0x0444 0x061C 0x8 0x1
+#define MX6UL_PAD_SD1_CMD__USDHC1_CMD                             0x01BC 0x0448 0x0000 0x0 0x0
+#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1                          0x01BC 0x0448 0x0000 0x1 0x0
+#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC                           0x01BC 0x0448 0x0000 0x2 0x0
+#define MX6UL_PAD_SD1_CMD__SPDIF_OUT                              0x01BC 0x0448 0x0000 0x3 0x0
+#define MX6UL_PAD_SD1_CMD__EIM_ADDR19                             0x01BC 0x0448 0x0000 0x4 0x0
+#define MX6UL_PAD_SD1_CMD__GPIO2_IO16                             0x01BC 0x0448 0x0000 0x5 0x0
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00                       0x01BC 0x0448 0x0610 0x6 0x2
+#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR                           0x01BC 0x0448 0x0000 0x8 0x0
+#define MX6UL_PAD_SD1_CLK__USDHC1_CLK                             0x01C0 0x044C 0x0000 0x0 0x0
+#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2                          0x01C0 0x044C 0x0000 0x1 0x0
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK                              0x01C0 0x044C 0x05F0 0x2 0x1
+#define MX6UL_PAD_SD1_CLK__SPDIF_IN                               0x01C0 0x044C 0x0618 0x3 0x3
+#define MX6UL_PAD_SD1_CLK__EIM_ADDR20                             0x01C0 0x044C 0x0000 0x4 0x0
+#define MX6UL_PAD_SD1_CLK__GPIO2_IO17                             0x01C0 0x044C 0x0000 0x5 0x0
+#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC                            0x01C0 0x044C 0x0664 0x8 0x2
+#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0                         0x01C4 0x0450 0x0000 0x0 0x0
+#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3                        0x01C4 0x0450 0x0000 0x1 0x0
+#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC                         0x01C4 0x0450 0x05FC 0x2 0x1
+#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX                          0x01C4 0x0450 0x0000 0x3 0x0
+#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21                           0x01C4 0x0450 0x0000 0x4 0x0
+#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18                           0x01C4 0x0450 0x0000 0x5 0x0
+#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID                       0x01C4 0x0450 0x04B8 0x8 0x2
+#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1                         0x01C8 0x0454 0x0000 0x0 0x0
+#define MX6UL_PAD_SD1_DATA1__GPT2_CLK                             0x01C8 0x0454 0x05A0 0x1 0x1
+#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK                         0x01C8 0x0454 0x05F8 0x2 0x1
+#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX                          0x01C8 0x0454 0x0584 0x3 0x3
+#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22                           0x01C8 0x0454 0x0000 0x4 0x0
+#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19                           0x01C8 0x0454 0x0000 0x5 0x0
+#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR                         0x01C8 0x0454 0x0000 0x8 0x0
+#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2                         0x01CC 0x0458 0x0000 0x0 0x0
+#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1                        0x01CC 0x0458 0x0598 0x1 0x1
+#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA                         0x01CC 0x0458 0x05F4 0x2 0x1
+#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX                          0x01CC 0x0458 0x0000 0x3 0x0
+#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23                           0x01CC 0x0458 0x0000 0x4 0x0
+#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20                           0x01CC 0x0458 0x0000 0x5 0x0
+#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1                            0x01CC 0x0458 0x0000 0x6 0x0
+#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC                          0x01CC 0x0458 0x0660 0x8 0x2
+#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3                         0x01D0 0x045C 0x0000 0x0 0x0
+#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2                        0x01D0 0x045C 0x059C 0x1 0x1
+#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA                         0x01D0 0x045C 0x0000 0x2 0x0
+#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX                          0x01D0 0x045C 0x0588 0x3 0x3
+#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24                           0x01D0 0x045C 0x0000 0x4 0x0
+#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21                           0x01D0 0x045C 0x0000 0x5 0x0
+#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2                            0x01D0 0x045C 0x0000 0x6 0x0
+#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID                       0x01D0 0x045C 0x04BC 0x8 0x2
+#define MX6UL_PAD_CSI_MCLK__CSI_MCLK                              0x01D4 0x0460 0x0000 0x0 0x0
+#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B                           0x01D4 0x0460 0x0674 0x1 0x0
+#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B                         0x01D4 0x0460 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_MCLK__I2C1_SDA                              0x01D4 0x0460 0x05A8 0x3 0x0
+#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B                             0x01D4 0x0460 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17                            0x01D4 0x0460 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL                     0x01D4 0x0460 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX                          0x01D4 0x0460 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX                          0x01D4 0x0460 0x064C 0x8 0x0
+#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK                          0x01D8 0x0464 0x0528 0x0 0x1
+#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP                           0x01D8 0x0464 0x069C 0x1 0x2
+#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B                       0x01D8 0x0464 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL                            0x01D8 0x0464 0x05A4 0x3 0x2
+#define MX6UL_PAD_CSI_PIXCLK__EIM_OE                              0x01D8 0x0464 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18                          0x01D8 0x0464 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5                       0x01D8 0x0464 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX                        0x01D8 0x0464 0x064C 0x8 0x3
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX                        0x01D8 0x0464 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC                            0x01DC 0x0468 0x052C 0x0 0x0
+#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK                           0x01DC 0x0468 0x0670 0x1 0x0
+#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK                       0x01DC 0x0468 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA                             0x01DC 0x0468 0x05B0 0x3 0x0
+#define MX6UL_PAD_CSI_VSYNC__EIM_RW                               0x01DC 0x0468 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19                           0x01DC 0x0468 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT                             0x01DC 0x0468 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS                        0x01DC 0x0468 0x0648 0x8 0x0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS                        0x01DC 0x0468 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC                            0x01E0 0x046C 0x0524 0x0 0x0
+#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD                           0x01E0 0x046C 0x0678 0x1 0x0
+#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD                        0x01E0 0x046C 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL                             0x01E0 0x046C 0x05AC 0x3 0x0
+#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B                            0x01E0 0x046C 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20                           0x01E0 0x046C 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT                             0x01E0 0x046C 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS                        0x01E0 0x046C 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS                        0x01E0 0x046C 0x0648 0x8 0x1
+#define MX6UL_PAD_CSI_DATA00__CSI_DATA02                          0x01E4 0x0470 0x04C4 0x0 0x0
+#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0                        0x01E4 0x0470 0x067C 0x1 0x0
+#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B                    0x01E4 0x0470 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK                         0x01E4 0x0470 0x0544 0x3 0x0
+#define MX6UL_PAD_CSI_DATA00__EIM_AD00                            0x01E4 0x0470 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21                          0x01E4 0x0470 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT                        0x01E4 0x0470 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX                        0x01E4 0x0470 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX                        0x01E4 0x0470 0x0644 0x8 0x0
+#define MX6UL_PAD_CSI_DATA01__CSI_DATA03                          0x01E8 0x0474 0x04C8 0x0 0x0
+#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1                        0x01E8 0x0474 0x0680 0x1 0x0
+#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN                     0x01E8 0x0474 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0                          0x01E8 0x0474 0x0550 0x3 0x0
+#define MX6UL_PAD_CSI_DATA01__EIM_AD01                            0x01E8 0x0474 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22                          0x01E8 0x0474 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK                           0x01E8 0x0474 0x05E0 0x6 0x0
+#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX                        0x01E8 0x0474 0x0644 0x8 0x1
+#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX                        0x01E8 0x0474 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_DATA02__CSI_DATA04                          0x01EC 0x0478 0x04D8 0x0 0x1
+#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2                        0x01EC 0x0478 0x0684 0x1 0x2
+#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD                     0x01EC 0x0478 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI                         0x01EC 0x0478 0x054C 0x3 0x1
+#define MX6UL_PAD_CSI_DATA02__EIM_AD02                            0x01EC 0x0478 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23                          0x01EC 0x0478 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC                        0x01EC 0x0478 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS                       0x01EC 0x0478 0x0640 0x8 0x5
+#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS                       0x01EC 0x0478 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_DATA03__CSI_DATA05                          0x01F0 0x047C 0x04CC 0x0 0x0
+#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3                        0x01F0 0x047C 0x0688 0x1 0x0
+#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD                       0x01F0 0x047C 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO                         0x01F0 0x047C 0x0548 0x3 0x0
+#define MX6UL_PAD_CSI_DATA03__EIM_AD03                            0x01F0 0x047C 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24                          0x01F0 0x047C 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK                        0x01F0 0x047C 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS                       0x01F0 0x047C 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS                       0x01F0 0x047C 0x0640 0x8 0x0
+#define MX6UL_PAD_CSI_DATA04__CSI_DATA06                          0x01F4 0x0480 0x04DC 0x0 0x1
+#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4                        0x01F4 0x0480 0x068C 0x1 0x2
+#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK                      0x01F4 0x0480 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK                         0x01F4 0x0480 0x0534 0x3 0x1
+#define MX6UL_PAD_CSI_DATA04__EIM_AD04                            0x01F4 0x0480 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25                          0x01F4 0x0480 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC                        0x01F4 0x0480 0x05EC 0x6 0x1
+#define MX6UL_PAD_CSI_DATA04__USDHC1_WP                           0x01F4 0x0480 0x066C 0x8 0x2
+#define MX6UL_PAD_CSI_DATA05__CSI_DATA07                          0x01F8 0x0484 0x04E0 0x0 0x1
+#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5                        0x01F8 0x0484 0x0690 0x1 0x2
+#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B                    0x01F8 0x0484 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0                          0x01F8 0x0484 0x0540 0x3 0x1
+#define MX6UL_PAD_CSI_DATA05__EIM_AD05                            0x01F8 0x0484 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26                          0x01F8 0x0484 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK                        0x01F8 0x0484 0x05E8 0x6 0x1
+#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B                         0x01F8 0x0484 0x0668 0x8 0x2
+#define MX6UL_PAD_CSI_DATA06__CSI_DATA08                          0x01FC 0x0488 0x04E4 0x0 0x1
+#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6                        0x01FC 0x0488 0x0694 0x1 0x2
+#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN                     0x01FC 0x0488 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI                         0x01FC 0x0488 0x053C 0x3 0x1
+#define MX6UL_PAD_CSI_DATA06__EIM_AD06                            0x01FC 0x0488 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27                          0x01FC 0x0488 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA                        0x01FC 0x0488 0x05E4 0x6 0x1
+#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B                      0x01FC 0x0488 0x0000 0x8 0x0
+#define MX6UL_PAD_CSI_DATA07__CSI_DATA09                          0x0200 0x048C 0x04E8 0x0 0x1
+#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7                        0x0200 0x048C 0x0698 0x1 0x2
+#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD                     0x0200 0x048C 0x0000 0x2 0x0
+#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO                         0x0200 0x048C 0x0538 0x3 0x1
+#define MX6UL_PAD_CSI_DATA07__EIM_AD07                            0x0200 0x048C 0x0000 0x4 0x0
+#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28                          0x0200 0x048C 0x0000 0x5 0x0
+#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA                        0x0200 0x048C 0x0000 0x6 0x0
+#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT                      0x0200 0x048C 0x0000 0x8 0x0
 
 #endif /* __DTS_IMX6UL_PINFUNC_H */

diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index c5c05fd..769d289 100644 (file)
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -8,13 +8,14 @@
 
 #include <dt-bindings/clock/imx6ul-clock.h>
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "imx6ul-pinfunc.h"
 #include "skeleton.dtsi"
 
 / {
        aliases {
+               can0 = &flexcan1;
+               can1 = &flexcan2;
                ethernet0 = &fec1;
                ethernet1 = &fec2;
                gpio0 = &gpio1;
@@ -36,13 +37,11 @@
                serial5 = &uart6;
                serial6 = &uart7;
                serial7 = &uart8;
-               sai1 = &sai1;
-               sai2 = &sai2;
-               sai3 = &sai3;
-               spi0 = &ecspi1;
-               spi1 = &ecspi2;
-               spi2 = &ecspi3;
-               spi3 = &ecspi4;
+               spi0 = &qspi;
+               spi1 = &ecspi1;
+               spi2 = &ecspi2;
+               spi3 = &ecspi3;
+               spi4 = &ecspi4;
                usbphy0 = &usbphy1;
                usbphy1 = &usbphy2;
        };
@@ -58,12 +57,14 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        operating-points = <
                                /* kHz  uV */
+                               696000  1275000
                                528000  1175000
                                396000  1025000
                                198000  950000
                        >;
                        fsl,soc-operating-points = <
                                /* KHz  uV */
+                               696000  1275000
                                528000  1175000
                                396000  1175000
                                198000  1175000
@@ -79,12 +80,8 @@
                                 <&clks IMX6UL_CLK_PLL1>,
                                 <&clks IMX6UL_PLL1_BYPASS_SRC>,
                                 <&clks IMX6UL_CLK_OSC>;
-                       clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
-                                     "secondary_sel", "step", "pll1_sw",
-                                     "pll1_sys", "pll1_bypass", "pll1",
-                                     "pll1_bypass_src", "osc";
-                       arm-supply = <&reg_arm>;
-                       soc-supply = <&reg_soc>;
+                       clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m", "secondary_sel", "step",
+                                     "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc";
                };
        };
 
@@ -93,37 +90,44 @@
                #interrupt-cells = <3>;
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
-                     <0x00a02000 0x1000>,
-                     <0x00a04000 0x2000>,
-                     <0x00a06000 0x2000>;
+                     <0x00a02000 0x100>;
        };
 
-       ckil: clock-cli {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <32768>;
-               clock-output-names = "ckil";
-       };
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
 
-       osc: clock-osc {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <24000000>;
-               clock-output-names = "osc";
-       };
+               ckil: clock@0 {
+                       compatible = "fixed-clock";
+                       reg = <0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+                       clock-output-names = "ckil";
+               };
 
-       ipp_di0: clock-di0 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <0>;
-               clock-output-names = "ipp_di0";
-       };
+               osc: clock@1 {
+                       compatible = "fixed-clock";
+                       reg = <1>;
+                       #clock-cells = <0>;
+                       clock-frequency = <24000000>;
+                       clock-output-names = "osc";
+               };
+
+               ipp_di0: clock@2 {
+                       compatible = "fixed-clock";
+                       reg = <2>;
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+                       clock-output-names = "ipp_di0";
+               };
 
-       ipp_di1: clock-di1 {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <0>;
-               clock-output-names = "ipp_di1";
+               ipp_di1: clock@3 {
+                       compatible = "fixed-clock";
+                       reg = <3>;
+                       #clock-cells = <0>;
+                       clock-frequency = <0>;
+                       clock-output-names = "ipp_di1";
+               };
        };
 
        soc {
@@ -133,37 +137,79 @@
                interrupt-parent = <&gpc>;
                ranges;
 
+               busfreq {
+                       compatible = "fsl,imx_busfreq";
+                       clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
+                                <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
+                                <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
+                                <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
+                                <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
+                                <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
+                                <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
+                                <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
+                                <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>;
+                       clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
+                                     "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
+                                     "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
+                                     "step", "mmdc";
+                       fsl,max_ddr_freq = <400000000>;
+               };
+
                pmu {
                        compatible = "arm,cortex-a7-pmu";
                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
-               ocram: sram@00900000 {
+               caam_sm: caam-sm@00100000 {
+                       compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
+                       reg = <0x00100000 0x3fff>;
+               };
+
+               irq_sec_vio: caam_secvio {
+                       compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
+                       interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                       jtag-tamper = "disabled";
+                       watchdog-tamper = "enabled";
+                       internal-boot-tamper = "enabled";
+                       external-pin-tamper = "disabled";
+               };
+
+               ocrams: sram@00900000 {
+                       compatible = "fsl,lpm-sram";
+                       reg = <0x00900000 0x4000>;
+               };
+
+               ocrams_ddr: sram@00904000 {
+                       compatible = "fsl,ddr-lpm-sram";
+                       reg = <0x00904000 0x1000>;
+               };
+
+               ocram: sram@00905000 {
                        compatible = "mmio-sram";
-                       reg = <0x00900000 0x20000>;
+                       reg = <0x00905000 0x1B000>;
                };
 
                dma_apbh: dma-apbh@01804000 {
-                       compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+                       compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh";
                        reg = <0x01804000 0x2000>;
-                       interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
-                                    <0 13 IRQ_TYPE_LEVEL_HIGH>,
-                                    <0 13 IRQ_TYPE_LEVEL_HIGH>,
-                                    <0 13 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
                        #dma-cells = <1>;
                        dma-channels = <4>;
                        clocks = <&clks IMX6UL_CLK_APBHDMA>;
                };
 
-               gpmi: gpmi-nand@01806000         {
-                       compatible = "fsl,imx6q-gpmi-nand";
+               gpmi: gpmi-nand@01806000{
+                       compatible = "fsl,imx6ul-gpmi-nand";
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
+                       reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
                        reg-names = "gpmi-nand", "bch";
-                       interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "bch";
                        clocks = <&clks IMX6UL_CLK_GPMI_IO>,
                                 <&clks IMX6UL_CLK_GPMI_APB>,
@@ -191,6 +237,28 @@
                                reg = <0x02000000 0x40000>;
                                ranges;
 
+                               spdif: spdif@02004000 {
+                                       compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif";
+                                       reg = <0x02004000 0x4000>;
+                                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                                       dmas = <&sdma 41 18 0>,
+                                              <&sdma 42 18 0>;
+                                       dma-names = "rx", "tx";
+                                       clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>,
+                                                <&clks IMX6UL_CLK_OSC>,
+                                                <&clks IMX6UL_CLK_SPDIF>,
+                                                <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
+                                                <&clks IMX6UL_CLK_IPG>,
+                                                <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
+                                                <&clks IMX6UL_CLK_SPBA>;
+                                       clock-names = "core", "rxtx0",
+                                                     "rxtx1", "rxtx2",
+                                                     "rxtx3", "rxtx4",
+                                                     "rxtx5", "rxtx6",
+                                                     "rxtx7", "dma";
+                                       status = "disabled";
+                               };
+
                                ecspi1: ecspi@02008000 {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
@@ -200,6 +268,8 @@
                                        clocks = <&clks IMX6UL_CLK_ECSPI1>,
                                                 <&clks IMX6UL_CLK_ECSPI1>;
                                        clock-names = "ipg", "per";
+                                       dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+                                       dma-names = "rx", "tx";
                                        status = "disabled";
                                };
 
@@ -212,6 +282,8 @@
                                        clocks = <&clks IMX6UL_CLK_ECSPI2>,
                                                 <&clks IMX6UL_CLK_ECSPI2>;
                                        clock-names = "ipg", "per";
+                                       dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
+                                       dma-names = "rx", "tx";
                                        status = "disabled";
                                };
 
@@ -224,6 +296,8 @@
                                        clocks = <&clks IMX6UL_CLK_ECSPI3>,
                                                 <&clks IMX6UL_CLK_ECSPI3>;
                                        clock-names = "ipg", "per";
+                                       dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
+                                       dma-names = "rx", "tx";
                                        status = "disabled";
                                };
 
@@ -236,23 +310,27 @@
                                        clocks = <&clks IMX6UL_CLK_ECSPI4>,
                                                 <&clks IMX6UL_CLK_ECSPI4>;
                                        clock-names = "ipg", "per";
+                                       dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
+                                       dma-names = "rx", "tx";
                                        status = "disabled";
                                };
 
                                uart7: serial@02018000 {
                                        compatible = "fsl,imx6ul-uart",
-                                                    "fsl,imx6q-uart";
+                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02018000 0x4000>;
                                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6UL_CLK_UART7_IPG>,
                                                 <&clks IMX6UL_CLK_UART7_SERIAL>;
                                        clock-names = "ipg", "per";
+                                       dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
+                                       dma-names = "rx", "tx";
                                        status = "disabled";
                                };
 
                                uart1: serial@02020000 {
                                        compatible = "fsl,imx6ul-uart",
-                                                    "fsl,imx6q-uart";
+                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02020000 0x4000>;
                                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6UL_CLK_UART1_IPG>,
@@ -263,59 +341,86 @@
 
                                uart8: serial@02024000 {
                                        compatible = "fsl,imx6ul-uart",
-                                                    "fsl,imx6q-uart";
+                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02024000 0x4000>;
                                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6UL_CLK_UART8_IPG>,
                                                 <&clks IMX6UL_CLK_UART8_SERIAL>;
                                        clock-names = "ipg", "per";
+                                       dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
+                                       dma-names = "rx", "tx";
                                        status = "disabled";
                                };
 
                                sai1: sai@02028000 {
-                                       #sound-dai-cells = <0>;
-                                       compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+                                       compatible = "fsl,imx6ul-sai",
+                                                    "fsl,imx6sx-sai";
                                        reg = <0x02028000 0x4000>;
                                        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
+                                                <&clks IMX6UL_CLK_DUMMY>,
                                                 <&clks IMX6UL_CLK_SAI1>,
-                                                <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
-                                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                       dmas = <&sdma 35 24 0>,
-                                              <&sdma 36 24 0>;
+                                                <&clks 0>, <&clks 0>;
+                                       clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
                                        dma-names = "rx", "tx";
+                                       dmas = <&sdma 35 24 0>, <&sdma 36 24 0>;
                                        status = "disabled";
                                };
 
                                sai2: sai@0202c000 {
-                                       #sound-dai-cells = <0>;
-                                       compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+                                       compatible = "fsl,imx6ul-sai",
+                                                    "fsl,imx6sx-sai";
                                        reg = <0x0202c000 0x4000>;
                                        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
+                                                <&clks IMX6UL_CLK_DUMMY>,
                                                 <&clks IMX6UL_CLK_SAI2>,
-                                                <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
-                                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                       dmas = <&sdma 37 24 0>,
-                                              <&sdma 38 24 0>;
+                                                <&clks 0>, <&clks 0>;
+                                       clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
                                        dma-names = "rx", "tx";
+                                       dmas = <&sdma 37 24 0>, <&sdma 38 24 0>;
                                        status = "disabled";
                                };
 
                                sai3: sai@02030000 {
-                                       #sound-dai-cells = <0>;
-                                       compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
+                                       compatible = "fsl,imx6ul-sai",
+                                                    "fsl,imx6sx-sai";
                                        reg = <0x02030000 0x4000>;
                                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
+                                                <&clks IMX6UL_CLK_DUMMY>,
                                                 <&clks IMX6UL_CLK_SAI3>,
-                                                <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
-                                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                       dmas = <&sdma 39 24 0>,
-                                              <&sdma 40 24 0>;
+                                                <&clks 0>, <&clks 0>;
+                                       clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
                                        dma-names = "rx", "tx";
+                                       dmas = <&sdma 39 24 0>, <&sdma 40 24 0>;
                                        status = "disabled";
                                };
+
+                               asrc: asrc@02034000 {
+                                       compatible = "fsl,imx53-asrc";
+                                       reg = <0x02034000 0x4000>;
+                                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                                       clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
+                                               <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
+                                               <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+                                               <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+                                               <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+                                               <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
+                                               <&clks IMX6UL_CLK_SPBA>;
+                                       clock-names = "mem", "ipg", "asrck_0",
+                                               "asrck_1", "asrck_2", "asrck_3", "asrck_4",
+                                               "asrck_5", "asrck_6", "asrck_7", "asrck_8",
+                                               "asrck_9", "asrck_a", "asrck_b", "asrck_c",
+                                               "asrck_d", "asrck_e", "asrck_f", "dma";
+                                       dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
+                                               <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
+                                       dma-names = "rxa", "rxb", "rxc",
+                                                   "txa", "txb", "txc";
+                                       fsl,asrc-rate  = <48000>;
+                                       fsl,asrc-width = <16>;
+                                       status = "okay";
+                               };
                        };
 
                        tsc: tsc@02040000 {
@@ -329,72 +434,77 @@
                                status = "disabled";
                        };
 
+                       bee: bee@02044000 {
+                               compatible = "fsl,imx6ul-bee";
+                               reg = <0x02044000 0x4000>;
+                               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                               status = "disabled";
+                       };
+
                        pwm1: pwm@02080000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x02080000 0x4000>;
-                               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_PWM1>,
                                         <&clks IMX6UL_CLK_PWM1>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
 
                        pwm2: pwm@02084000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x02084000 0x4000>;
-                               interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_PWM2>,
-                                        <&clks IMX6UL_CLK_PWM2>;
+                               interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
 
                        pwm3: pwm@02088000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x02088000 0x4000>;
-                               interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_PWM3>,
-                                        <&clks IMX6UL_CLK_PWM3>;
+                               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
 
                        pwm4: pwm@0208c000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x0208c000 0x4000>;
-                               interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_PWM4>,
-                                        <&clks IMX6UL_CLK_PWM4>;
+                               interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
 
-                       can1: flexcan@02090000 {
+                       flexcan1: can@02090000 {
                                compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
                                reg = <0x02090000 0x4000>;
                                interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
                                         <&clks IMX6UL_CLK_CAN1_SERIAL>;
                                clock-names = "ipg", "per";
+                               stop-mode = <&gpr 0x10 1 0x10 17>;
                                status = "disabled";
                        };
 
-                       can2: flexcan@02094000 {
+                       flexcan2: can@02094000 {
                                compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
                                reg = <0x02094000 0x4000>;
                                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
                                         <&clks IMX6UL_CLK_CAN2_SERIAL>;
                                clock-names = "ipg", "per";
+                               stop-mode = <&gpr 0x10 2 0x10 18>;
                                status = "disabled";
                        };
 
                        gpt1: gpt@02098000 {
-                               compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
+                               compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
                                reg = <0x02098000 0x4000>;
                                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
@@ -411,8 +521,6 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
-                                             <&iomuxc 16 33 16>;
                        };
 
                        gpio2: gpio@020a0000 {
@@ -424,7 +532,6 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
                        };
 
                        gpio3: gpio@020a4000 {
@@ -436,7 +543,6 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               gpio-ranges = <&iomuxc 0 65 29>;
                        };
 
                        gpio4: gpio@020a8000 {
@@ -448,7 +554,6 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
                        };
 
                        gpio5: gpio@020ac000 {
@@ -460,7 +565,12 @@
                                #gpio-cells = <2>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
+                       };
+
+                       snvslp: snvs@020b0000 {
+                               compatible = "fsl,imx6ul-snvs";
+                               reg = <0x020b0000 0x4000>;
+                               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
                        };
 
                        fec2: ethernet@020b4000 {
@@ -475,16 +585,19 @@
                                         <&clks IMX6UL_CLK_ENET2_REF_125M>;
                                clock-names = "ipg", "ahb", "ptp",
                                              "enet_clk_ref", "enet_out";
+                               stop-mode = <&gpr 0x10 4>;
                                fsl,num-tx-queues=<1>;
                                fsl,num-rx-queues=<1>;
+                               fsl,magic-packet;
+                               fsl,wakeup_irq = <0>;
                                status = "disabled";
                        };
 
                        kpp: kpp@020b8000 {
-                               compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
+                               compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
                                reg = <0x020b8000 0x4000>;
                                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_KPP>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>;
                                status = "disabled";
                        };
 
@@ -521,7 +634,7 @@
                                             <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 
-                               reg_3p0: regulator-3p0 {
+                               reg_3p0: regulator-3p0@120 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
                                        regulator-min-microvolt = <2625000>;
@@ -535,7 +648,7 @@
                                        anatop-enable-bit = <0>;
                                };
 
-                               reg_arm: regulator-vddcore {
+                               reg_arm: regulator-vddcore@140 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "cpu";
                                        regulator-min-microvolt = <725000>;
@@ -552,7 +665,7 @@
                                        anatop-max-voltage = <1450000>;
                                };
 
-                               reg_soc: regulator-vddsoc {
+                               reg_soc: regulator-vddsoc@140 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddsoc";
                                        regulator-min-microvolt = <725000>;
@@ -588,6 +701,19 @@
                                fsl,anatop = <&anatop>;
                        };
 
+                       tempmon: tempmon {
+                               compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
+                               interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                               fsl,tempmon = <&anatop>;
+                               fsl,tempmon-data = <&ocotp>;
+                               clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
+                       };
+
+                       caam_snvs: caam-snvs@020cc000 {
+                               compatible = "fsl,imx6q-caam-snvs";
+                               reg = <0x020cc000 0x4000>;
+                       };
+
                        snvs: snvs@020cc000 {
                                compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
                                reg = <0x020cc000 0x4000>;
@@ -596,16 +722,14 @@
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        regmap = <&snvs>;
                                        offset = <0x34>;
-                                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-                                                    <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                                };
 
                                snvs_poweroff: snvs-poweroff {
                                        compatible = "syscon-poweroff";
                                        regmap = <&snvs>;
                                        offset = <0x38>;
-                                       mask = <0x60>;
-                                       status = "disabled";
+                                       mask = <0x61>;
                                };
 
                                snvs_pwrkey: snvs-powerkey {
@@ -613,7 +737,7 @@
                                        regmap = <&snvs>;
                                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
                                        linux,keycode = <KEY_POWER>;
-                                       wakeup-source;
+                                       wakeup;
                                };
                        };
 
@@ -642,6 +766,7 @@
                                #interrupt-cells = <3>;
                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-parent = <&intc>;
+                               fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
                        };
 
                        iomuxc: iomuxc@020e0000 {
@@ -651,28 +776,34 @@
 
                        gpr: iomuxc-gpr@020e4000 {
                                compatible = "fsl,imx6ul-iomuxc-gpr",
-                                            "fsl,imx6q-iomuxc-gpr", "syscon";
+                                       "fsl,imx6q-iomuxc-gpr", "syscon";
                                reg = <0x020e4000 0x4000>;
                        };
 
+                       mqs: mqs {
+                               compatible = "fsl,imx6sx-mqs";
+                               gpr = <&gpr>;
+                               status = "disabled";
+                       };
+
                        gpt2: gpt@020e8000 {
-                               compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
+                               compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt";
                                reg = <0x020e8000 0x4000>;
                                interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
-                                        <&clks IMX6UL_CLK_GPT2_SERIAL>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                        };
 
                        sdma: sdma@020ec000 {
-                               compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
-                                            "fsl,imx35-sdma";
+                               compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
                                reg = <0x020ec000 0x4000>;
                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_SDMA>,
                                         <&clks IMX6UL_CLK_SDMA>;
                                clock-names = "ipg", "ahb";
                                #dma-cells = <3>;
+                               iram = <&ocram>;
                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
                        };
 
@@ -680,44 +811,40 @@
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020f0000 0x4000>;
                                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_PWM5>,
-                                        <&clks IMX6UL_CLK_PWM5>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
 
                        pwm6: pwm@020f4000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020f4000 0x4000>;
                                interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_PWM6>,
-                                        <&clks IMX6UL_CLK_PWM6>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
 
                        pwm7: pwm@020f8000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020f8000 0x4000>;
                                interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_PWM7>,
-                                        <&clks IMX6UL_CLK_PWM7>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
 
                        pwm8: pwm@020fc000 {
                                compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
                                reg = <0x020fc000 0x4000>;
                                interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-                               clocks = <&clks IMX6UL_CLK_PWM8>,
-                                        <&clks IMX6UL_CLK_PWM8>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
                                clock-names = "ipg", "per";
                                #pwm-cells = <2>;
-                               status = "disabled";
                        };
                };
 
@@ -728,6 +855,35 @@
                        reg = <0x02100000 0x100000>;
                        ranges;
 
+                       crypto: caam@2140000 {
+                               compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0x2140000 0x3c000>;
+                               ranges = <0 0x2140000 0x3c000>;
+                               interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
+                                        <&clks IMX6UL_CLK_CAAM_MEM>;
+                               clock-names = "caam_ipg", "caam_aclk", "caam_mem";
+
+                               sec_jr0: jr0@1000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x1000 0x1000>;
+                                       interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+
+                               sec_jr1: jr1@2000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x2000 0x1000>;
+                                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+                               sec_jr2: jr2@3000 {
+                                       compatible = "fsl,sec-v4.0-job-ring";
+                                       reg = <0x3000 0x1000>;
+                                       interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                               };
+                       };
+
                        usbotg1: usb@02184000 {
                                compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
                                reg = <0x02184000 0x200>;
@@ -773,8 +929,18 @@
                                         <&clks IMX6UL_CLK_ENET_REF>;
                                clock-names = "ipg", "ahb", "ptp",
                                              "enet_clk_ref", "enet_out";
+                               stop-mode = <&gpr 0x10 3>;
                                fsl,num-tx-queues=<1>;
                                fsl,num-rx-queues=<1>;
+                               fsl,magic-packet;
+                               fsl,wakeup_irq = <0>;
+                               status = "disabled";
+                        };
+
+                       sim1: sim@0218c000 {
+                               compatible = "fsl,imx6ul-sim";
+                               reg = <0x0218c000 0x4000>;
+                               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                                status = "disabled";
                        };
 
@@ -809,10 +975,8 @@
                                clocks = <&clks IMX6UL_CLK_ADC1>;
                                num-channels = <2>;
                                clock-names = "adc";
-                               fsl,adck-max-frequency = <30000000>, <40000000>,
-                                                        <20000000>;
                                status = "disabled";
-                       };
+                        };
 
                        i2c1: i2c@021a0000 {
                                #address-cells = <1>;
@@ -844,11 +1008,56 @@
                                status = "disabled";
                        };
 
+                       romcp@021ac000 {
+                               compatible = "fsl,imx6ul-romcp", "syscon";
+                               reg = <0x021ac000 0x4000>;
+                       };
+
                        mmdc: mmdc@021b0000 {
                                compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;
                        };
 
+                       sim2: sim@021b4000 {
+                               compatible = "fsl,imx6ul-sim";
+                               reg = <0x021b4000 0x4000>;
+                               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_SIM2>;
+                               clock-names = "sim";
+                               status = "disabled";
+                       };
+
+                       weim: weim@021b8000 {
+                               compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
+                               reg = <0x021b8000 0x4000>;
+                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>;
+                       };
+
+                       ocotp: ocotp-ctrl@021bc000 {
+                               compatible = "fsl,imx6ul-ocotp", "syscon";
+                               reg = <0x021bc000 0x4000>;
+                               clocks = <&clks IMX6UL_CLK_OCOTP>;
+                       };
+
+                       csu: csu@021c0000 {
+                               compatible = "fsl,imx6ul-csu";
+                               reg = <0x021c0000 0x4000>;
+                               interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                               status = "disabled";
+                       };
+
+                       csi: csi@021c4000 {
+                               compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi";
+                               reg = <0x021c4000 0x4000>;
+                               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_DUMMY>,
+                                       <&clks IMX6UL_CLK_CSI>,
+                                       <&clks IMX6UL_CLK_DUMMY>;
+                               clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+                               status = "disabled";
+                       };
+
                        lcdif: lcdif@021c8000 {
                                compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
                                reg = <0x021c8000 0x4000>;
@@ -860,10 +1069,20 @@
                                status = "disabled";
                        };
 
+                       pxp: pxp@021cc000 {
+                               compatible = "fsl,imx6ul-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
+                               reg = <0x021cc000 0x4000>;
+                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clks IMX6UL_CLK_PXP>,
+                                        <&clks IMX6UL_CLK_DUMMY>;
+                               clock-names = "pxp-axi", "disp-axi";
+                               status = "disabled";
+                       };
+
                        qspi: qspi@021e0000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
+                               compatible = "fsl,imx6ul-qspi";
                                reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
                                reg-names = "QuadSPI", "QuadSPI-memory";
                                interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
@@ -875,45 +1094,53 @@
 
                        uart2: serial@021e8000 {
                                compatible = "fsl,imx6ul-uart",
-                                            "fsl,imx6q-uart";
+                                            "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021e8000 0x4000>;
                                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_UART2_IPG>,
                                         <&clks IMX6UL_CLK_UART2_SERIAL>;
                                clock-names = "ipg", "per";
+                               dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
                        uart3: serial@021ec000 {
                                compatible = "fsl,imx6ul-uart",
-                                            "fsl,imx6q-uart";
+                                            "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021ec000 0x4000>;
                                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_UART3_IPG>,
                                         <&clks IMX6UL_CLK_UART3_SERIAL>;
                                clock-names = "ipg", "per";
+                               dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
                        uart4: serial@021f0000 {
                                compatible = "fsl,imx6ul-uart",
-                                            "fsl,imx6q-uart";
+                                            "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f0000 0x4000>;
                                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_UART4_IPG>,
                                         <&clks IMX6UL_CLK_UART4_SERIAL>;
                                clock-names = "ipg", "per";
+                               dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
                        uart5: serial@021f4000 {
                                compatible = "fsl,imx6ul-uart",
-                                            "fsl,imx6q-uart";
+                                            "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f4000 0x4000>;
                                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_UART5_IPG>,
                                         <&clks IMX6UL_CLK_UART5_SERIAL>;
                                clock-names = "ipg", "per";
+                               dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
 
@@ -929,12 +1156,14 @@
 
                        uart6: serial@021fc000 {
                                compatible = "fsl,imx6ul-uart",
-                                            "fsl,imx6q-uart";
+                                            "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021fc000 0x4000>;
                                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6UL_CLK_UART6_IPG>,
                                         <&clks IMX6UL_CLK_UART6_SERIAL>;
                                clock-names = "ipg", "per";
+                               dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
+                               dma-names = "rx", "tx";
                                status = "disabled";
                        };
                };