MLK-15978 arm64: dts: imx8: change can clock rate to 40Mhz
authorDong Aisheng <aisheng.dong@nxp.com>
Thu, 13 Jul 2017 12:40:25 +0000 (20:40 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 20:36:12 +0000 (15:36 -0500)
CAN needs at least 40Mhz PE clock rate to support CAN FD well.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi

index 54b05e1..5482506 100644 (file)
                         <&clk IMX8QM_CAN0_CLK>;
                clock-names = "ipg", "per";
                assigned-clocks = <&clk IMX8QM_CAN0_CLK>;
-               assigned-clock-rates = <24000000>;
+               assigned-clock-rates = <40000000>;
                power-domains = <&pd_dma_flexcan0>;
                status = "disabled";
        };
                         <&clk IMX8QM_CAN1_CLK>;
                clock-names = "ipg", "per";
                assigned-clocks = <&clk IMX8QM_CAN1_CLK>;
-               assigned-clock-rates = <24000000>;
+               assigned-clock-rates = <40000000>;
                power-domains = <&pd_dma_flexcan1>;
                status = "disabled";
        };
                         <&clk IMX8QM_CAN2_CLK>;
                clock-names = "ipg", "per";
                assigned-clocks = <&clk IMX8QM_CAN2_CLK>;
-               assigned-clock-rates = <24000000>;
+               assigned-clock-rates = <40000000>;
                power-domains = <&pd_dma_flexcan2>;
                status = "disabled";
        };
index 71c86c1..787c229 100644 (file)
                         <&clk IMX8QXP_CAN0_CLK>;
                clock-names = "ipg", "per";
                assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
-               assigned-clock-rates = <24000000>;
+               assigned-clock-rates = <40000000>;
                power-domains = <&pd_dma_flexcan0>;
                status = "disabled";
        };
                         <&clk IMX8QXP_CAN0_CLK>;
                clock-names = "ipg", "per";
                assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
-               assigned-clock-rates = <24000000>;
+               assigned-clock-rates = <40000000>;
                power-domains = <&pd_dma_flexcan0>;
                status = "disabled";
        };
                         <&clk IMX8QXP_CAN0_CLK>;
                clock-names = "ipg", "per";
                assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
-               assigned-clock-rates = <24000000>;
+               assigned-clock-rates = <40000000>;
                power-domains = <&pd_dma_flexcan0>;
                status = "disabled";
        };