MLK-21834-1 DTS: Update iMX8QXP MEK board DTS

Add i2c alias for i2c mux bus, add mipi lvds i2c nodes, usbotg1, usbotg3,
fec, flexspi, and update iomux.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f4dfbce84dfefbed11dab45908caf44d616ddca7)

diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 701af44..c82a2c7 100644 (file)
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -3,6 +3,20 @@
  * Copyright 2018 NXP
  */
 
+/ {
+
+       aliases {
+               usbhost1 = &usbh3;
+       };
+
+       usbh3: usbh3 {
+               compatible = "Cadence,usb3-host";
+               dr_mode = "host";
+               cdns3,usb = <&usbotg3>;
+               status = "okay";
+       };
+};
+
 &{/imx8qx-pm} {
 
        u-boot,dm-spl;
@@ -20,6 +34,38 @@
        u-boot,dm-spl;
 };
 
+&{/regulators} {
+       u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+       u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qxp-mek} {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+       u-boot,dm-spl;
+};
+
 &pd_lsio {
        u-boot,dm-spl;
 };
@@ -80,6 +126,18 @@
        u-boot,dm-spl;
 };
 
+&pd_lsio_flexspi0 {
+       u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+       u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+       u-boot,dm-spl;
+};
+
 &gpio0 {
        u-boot,dm-spl;
 };
@@ -116,6 +174,18 @@
        u-boot,dm-spl;
 };
 
+&usbotg3 {
+       phys = <&usbphynop1>;
+       u-boot,dm-spl;
+};
+
+&usbphynop1 {
+       compatible = "cdns,usb3-phy";
+       reg = <0x0 0x5B160000 0x0 0x40000>;
+       #phy-cells = <0>;
+       u-boot,dm-spl;
+};
+
 &usdhc1 {
        u-boot,dm-spl;
        mmc-hs400-1_8v;
@@ -126,3 +196,39 @@
        sd-uhs-sdr104;
        sd-uhs-ddr50;
 };
+
+&flexspi0 {
+       u-boot,dm-spl;
+};
+
+&flash0 {
+       u-boot,dm-spl;
+};
+
+&wu {
+       u-boot,dm-spl;
+};
+
+&fec1 {
+       phy-mode = "rgmii-id";
+};
+
+&fec2 {
+       phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+       vddio0: vddio-regulator {
+               regulator-name = "VDDIO";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+};
+
+&ethphy1 {
+       vddio1: vddio-regulator {
+               regulator-name = "VDDIO";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+};
\ No newline at end of file

diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index 4f35fbe..f2d82a5 100644 (file)
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -6,25 +6,50 @@
 /dts-v1/;
 
 #include "fsl-imx8qxp.dtsi"
-#include "fsl-imx8qxp-mek-u-boot.dtsi"
 
 / {
-       model = "Freescale i.MX8QXP MEK";
+       model = "NXP i.MX8QXP MEK";
        compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
 
+       aliases {
+               i2c4 = &bb_i2c1;
+               i2c5 = &mfi_i2c1;
+               i2c6 = &i2cexp1_i2c1;
+               i2c7 = &i2cexp2_i2c1;
+               gpio8 = &pca9557_a;
+               gpio9 = &pca9557_b;
+       };
+
        chosen {
-               bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+               bootargs = "console=ttyLP0,115200 earlycon";
                stdout-path = &lpuart0;
        };
 
-       reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
-               compatible = "regulator-fixed";
-               regulator-name = "SD1_SPWR";
-               regulator-min-microvolt = <3000000>;
-               regulator-max-microvolt = <3000000>;
-               gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
-               off-on-delay = <3480>;
-               enable-active-high;
+       regulators {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+                       compatible = "regulator-fixed";
+                       regulator-name = "SD1_SPWR";
+                       regulator-min-microvolt = <3000000>;
+                       regulator-max-microvolt = <3000000>;
+                       gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+                       off-on-delay-us = <3480>;
+               };
+
+               reg_usb_otg1_vbus: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "usb_otg1_vbus";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>;
+                       enable-active-high;
+               };
+
        };
 };
 
@@ -40,45 +65,41 @@
                        >;
                };
 
-               pinctrl_ioexp_rst: ioexp-rst-grp {
-                       fsl,pins = <
-                               SC_P_SPI2_SDO_LSIO_GPIO1_IO01   0x06000021
-                       >;
-               };
-
                pinctrl_fec1: fec1grp {
                        fsl,pins = <
-                               SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000048
-                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000048
-                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
-                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x06000048
-                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x06000048
-                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x06000048
-                               SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x06000048
-                               SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x06000048
-                               SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x06000048
-                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
-                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x06000048
-                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x06000048
-                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x06000048
-                               SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x06000048
+                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      0x000014a0
+                               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      0x000014a0
+                               SC_P_ENET0_MDC_CONN_ENET0_MDC                   0x06000020
+                               SC_P_ENET0_MDIO_CONN_ENET0_MDIO                 0x06000020
+                               SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
+                               SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC       0x00000061
+                               SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0     0x00000061
+                               SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1     0x00000061
+                               SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2     0x00000061
+                               SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3     0x00000061
+                               SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC       0x00000061
+                               SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
+                               SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0     0x00000061
+                               SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1     0x00000061
+                               SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2     0x00000061
+                               SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3     0x00000061
                        >;
                };
 
                pinctrl_fec2: fec2grp {
                        fsl,pins = <
-                               SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x06000048
-                               SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC             0x06000048
-                               SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x06000048
-                               SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x06000048
-                               SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2            0x06000048
-                               SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3           0x06000048
-                               SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC             0x06000048
-                               SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x06000048
-                               SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x06000048
-                               SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x06000048
-                               SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2        0x06000048
-                               SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3            0x06000048
+                               SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL         0x00000060
+                               SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC             0x00000060
+                               SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0        0x00000060
+                               SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1        0x00000060
+                               SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2            0x00000060
+                               SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3           0x00000060
+                               SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC             0x00000060
+                               SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL          0x00000060
+                               SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0            0x00000060
+                               SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1        0x00000060
+                               SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2        0x00000060
+                               SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3            0x00000060
                        >;
                };
 
@@ -131,6 +152,41 @@
                                SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
                        >;
                };
+
+               pinctrl_flexspi0: flexspi0grp {
+                       fsl,pins = <
+                               SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
+                               SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
+                               SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
+                               SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
+                               SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
+                               SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
+                               SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B     0x06000021
+                               SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
+                               SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
+                               SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
+                               SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
+                               SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
+                               SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
+                               SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
+                               SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
+                               SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
+                       >;
+               };
+
+               pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
+                       fsl,pins = <
+                               SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
+                               SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
+                       >;
+               };
+
+               pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
+                       fsl,pins = <
+                               SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
+                               SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
+                       >;
+               };
        };
 };
 
@@ -144,18 +200,49 @@
        status = "okay";
 };
 
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio3 {
+       status = "okay";
+};
+
+&gpio4 {
+       status = "okay";
+};
+
+&flexspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       flash0: mt35xu512aba@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <29000000>;
+               spi-nor,ddr-quad-read-dummy = <8>;
+       };
+};
+
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
+       pinctrl-0 = <&pinctrl_lpi2c1>;
        status = "okay";
 
        i2cswitch@71 {
                compatible = "nxp,pca9646";
                reg = <0x71>;
+               u-boot,i2c-offset-len = <0>;
                #address-cells = <1>;
                #size-cells = <0>;
-               reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 
                bb_i2c1: i2c@0 {
                        #address-cells = <1>;
@@ -196,17 +283,39 @@
        };
 };
 
-&usdhc1 {
+&i2c0_mipi_lvds0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
        pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
+       clock-frequency = <100000>;
+       status = "okay";
+};
+
+&i2c0_mipi_lvds1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
+       clock-frequency = <100000>;
+       status = "okay";
+};
+
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1>;
+       pinctrl-2 = <&pinctrl_usdhc1>;
        bus-width = <8>;
        non-removable;
        status = "okay";
 };
 
 &usdhc2 {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
        bus-width = <4>;
        cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
        wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
@@ -240,3 +349,27 @@
                };
        };
 };
+
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec2>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy1>;
+       fsl,ar8031-phy-fixup;
+       fsl,magic-packet;
+       status = "okay";
+};
+
+&usbotg1 {
+       vbus-supply = <&reg_usb_otg1_vbus>;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       power-polarity-active-high;
+       disable-over-current;
+       status = "okay";
+};
+
+&usbotg3 {
+       status = "okay";
+};