MLK-22832 board: imx8mn_evk: Fix the retention hang on imx8mn lpddr4 evk

The '0x20060' register is used for phy memory reset, should not be put
in the ddrphy config section, so remove it from the timing script,
otherwise, ddr retention can NOT work. Additionally, the'0xd0000'
register config in phy section is redundant, remove it too.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 9d944032008fb37850aeb3d83f7de4e659fad319)
(cherry picked from commit 75e87a0af9b81d0b6c98234c8e33396360b3c629)
(cherry picked from commit f3dc8af4b6fe1bd6ade5c2d45df0ca11beeec5e0)

diff --git a/board/freescale/imx8mn_evk/lpddr4_timing.c b/board/freescale/imx8mn_evk/lpddr4_timing.c
index 671e924..0ce039a 100644 (file)
--- a/board/freescale/imx8mn_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mn_evk/lpddr4_timing.c
@@ -122,7 +122,6 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 
 /* PHY Initialize Configuration */
 struct dram_cfg_param ddr_ddrphy_cfg[] = {
-       {0x000d0000, 0x00000000},
        {0x000100a0, 0x00000000},
        {0x000100a1, 0x00000001},
        {0x000100a2, 0x00000002},
@@ -271,8 +270,6 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
        {0x002200c7, 0x00000021},
        {0x002200ca, 0x00000024},
        {0x002200cc, 0x000001f7},
-       {0x00020060, 0x00000002},
-       {0x000d0000, 0x00000001},
 };
 
 /* ddr phy trained csr */