#define ASRC_FIFO_THRESHOLD_MAX 63
#define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
#define ASRC_MAX_BUFFER_SIZE (1024 * 48)
-#define ASRC_OUTPUT_LAST_SAMPLE 8
+#define ASRC_OUTPUT_LAST_SAMPLE_MAX 32
+#define ASRC_OUTPUT_LAST_SAMPLE 16
#define IDEAL_RATIO_RATE 1000000
enum asrc_word_width word_width[2];
unsigned int rate[2];
+ unsigned int last_period_size;
u32 watermark[2];
spinlock_t lock;
};
if (size)
goto retry;
- if (t_size > ASRC_OUTPUT_LAST_SAMPLE)
- t_size = ASRC_OUTPUT_LAST_SAMPLE;
+ if (t_size > m2m->last_period_size)
+ t_size = m2m->last_period_size;
if (reg24)
output->length += t_size * pair->channels * 4;
slave_config.dst_addr = dma_addr;
slave_config.dst_addr_width = buswidth;
slave_config.dst_maxburst =
- m2m->watermark[IN] * pair->channels / buswidth;
+ m2m->watermark[IN] * pair->channels;
} else {
slave_config.direction = DMA_DEV_TO_MEM;
slave_config.src_addr = dma_addr;
slave_config.src_addr_width = buswidth;
slave_config.src_maxburst =
- m2m->watermark[OUT] * pair->channels / buswidth;
+ m2m->watermark[OUT] * pair->channels;
}
ret = dmaengine_slave_config(chan, &slave_config);
struct dma_chan *dma_chan = pair->dma_chan[dir];
unsigned int buf_len, wm = m2m->watermark[dir];
unsigned int *sg_nodes = &m2m->sg_nodes[dir];
+ unsigned int last_period_size = m2m->last_period_size;
enum asrc_pair_index index = pair->index;
u32 word_size, fifo_addr;
void __user *buf_vaddr;
*dma_len = buf_len;
if (dir == OUT)
- *dma_len -= ASRC_OUTPUT_LAST_SAMPLE * word_size * pair->channels;
+ *dma_len -= last_period_size * word_size * pair->channels;
*sg_nodes = *dma_len / ASRC_MAX_BUFFER_SIZE + 1;
m2m->rate[IN] = config.input_sample_rate;
m2m->rate[OUT] = config.output_sample_rate;
+ if (m2m->rate[OUT] > m2m->rate[IN])
+ m2m->last_period_size = ASRC_OUTPUT_LAST_SAMPLE_MAX;
+ else
+ m2m->last_period_size = ASRC_OUTPUT_LAST_SAMPLE;
+
ret = fsl_allocate_dma_buf(pair);
if (ret) {
pair_err("failed to allocate DMA buffer: %ld\n", ret);