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MLK-12792 ARM: dts: imx6ull-14x14-ddr3-arm2: improve enet clock timing
authorAndy Duan <fugang.duan@nxp.com>
Wed, 11 May 2016 06:47:18 +0000 (14:47 +0800)
committerLeonard Crestez <leonard.crestez@nxp.com>
Wed, 17 Apr 2019 23:31:07 +0000 (02:31 +0300)
Improve enet data/txc clock timing suggested by HW team.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts patch | blob | history

diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
index 93d6201..31e1bff 100644 (file)
--- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2.dts
@@ -480,18 +480,18 @@
                                MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
                                MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
                                MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
-                               MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b0a8
+                               MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b0a0
                        >;
                };
 
                pinctrl_enet2: enet2grp {
                        fsl,pins = <
-                               MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                               MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b098
                                MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
-                               MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
-                               MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
-                               MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02  0x1b0b0
-                               MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03  0x1b0b0
+                               MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
+                               MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
+                               MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02  0x1b0a0
+                               MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03  0x1b0a0
                                MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK    0x4001b0a8
                                MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
                                MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0