MLK-15070-3: ARM64: dts: enable audio codec on the audio board of mscale

Enable the AK4458, AK5558, and AK4497 with mode 0. For ak4497 use
same SAI interface with AK4458, so move ak4497 device node to
a separate dts.

The AK4458 support maximum 16 channels, the AK5558 support maximum 8
channels, AK4497 is for stereo.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 9c8ff7d..db48d8e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -48,7 +48,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \
                                 fsl-imx8mq-evk-pdm.dtb \
                                 fsl-imx8mq-evk-dcss-adv7535.dtb \
                                 fsl-imx8mq-evk-dcss-rm67191.dtb \
-                                fsl-imx8mq-evk-dual-display.dtb
+                                fsl-imx8mq-evk-dual-display.dtb \
+                                fsl-imx8mq-evk-ak4497.dtb
 
 always         := $(dtb-y)
 subdir-y       := $(dts-dirs)

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts
new file mode 100644 (file)
index 0000000..8045368
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8mq-evk.dts"
+
+/ {
+       sound-ak4458 {
+               status = "disabled";
+       };
+
+       sound-ak4497 {
+               status = "okay";
+       };
+};
+

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
index ba74705..c3ba8f0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
@@ -104,6 +104,28 @@
                spdif-controller = <&spdif2>;
                spdif-in;
        };
+
+       sound-ak4458 {
+               compatible = "fsl,imx-audio-ak4458";
+               model = "ak4458-audio";
+               audio-cpu = <&sai1>;
+               audio-codec = <&ak4458_1>, <&ak4458_2>;
+       };
+
+       sound-ak5558 {
+               compatible = "fsl,imx-audio-ak5558";
+               model = "ak5558-audio";
+               audio-cpu = <&sai5>;
+               audio-codec = <&ak5558>;
+       };
+
+       sound-ak4497 {
+               compatible = "fsl,imx-audio-ak4497";
+               model = "ak4497-audio";
+               audio-cpu = <&sai1>;
+               audio-codec = <&ak4497>;
+               status = "disabled";
+       };
 };
 
 &clk {
@@ -113,8 +135,17 @@
 
 &iomuxc {
        pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog>;
 
        imx8mq-evk {
+               pinctrl_hog: hoggrp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16            0x19
+                               MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17               0x19
+                               MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18               0x19
+                       >;
+               };
+
                pinctrl_csi1: csi1grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x19
@@ -164,6 +195,12 @@
                        >;
                };
 
+               pinctrl_i2c3: i2c3grp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x4000007f
+                               MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x4000007f
+                       >;
+               };
 
                pinctrl_pcie0: pcie0grp {
                        fsl,pins = <
@@ -317,6 +354,23 @@
                        >;
                };
 
+               pinctrl_sai1: sai1grp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK                0xd6
+                               MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC             0xd6
+                               MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC             0xd6
+                               MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK              0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0            0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1            0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2            0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3            0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4            0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5            0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6            0xd6
+                               MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7            0xd6
+                       >;
+               };
+
                pinctrl_sai2: sai2grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
@@ -327,6 +381,18 @@
                        >;
                };
 
+               pinctrl_sai5: sai5grp {
+                       fsl,pins = <
+                               MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK        0xd6
+                               MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK      0xd6
+                               MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC     0xd6
+                               MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0    0xd6
+                               MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC     0xd6
+                               MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK     0xd6
+                               MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0    0xd6
+                       >;
+               };
+
                pinctrl_spdif1: spdif1grp {
                        fsl,pins = <
                                MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT        0xd6
@@ -527,6 +593,36 @@
        status = "disabled";
 };
 
+&i2c3 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+
+       ak4458_1: ak4458@10 {
+               compatible = "asahi-kasei,ak4458";
+               reg = <0x10>;
+               ak4458,pdn-gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+       };
+
+       ak4458_2: ak4458@12 {
+               compatible = "asahi-kasei,ak4458";
+               reg = <0x12>;
+       };
+
+       ak5558: ak5558@13 {
+               compatible = "asahi-kasei,ak5558";
+               reg = <0x13>;
+               ak5558,pdn-gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+       };
+
+       ak4497: ak4497@11 {
+               compatible = "asahi-kasei,ak4497";
+               reg = <0x11>;
+               ak4497,pdn-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+       };
+};
+
 &pcie0{
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie0>;
@@ -629,6 +725,16 @@
        dr_mode = "host";
 };
 
+&sai1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai1>;
+       assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>,
+                       <&clk IMX8MQ_CLK_SAI1_DIV>;
+       assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <0>, <24576000>;
+       status = "okay";
+};
+
 &sai2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai2>;
@@ -647,6 +753,17 @@
        status = "okay";
 };
 
+&sai5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai5>;
+       assigned-clocks = <&clk IMX8MQ_CLK_SAI5_SRC>,
+                       <&clk IMX8MQ_CLK_SAI5_DIV>;
+       assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <0>, <24576000>;
+       fsl,sai-asynchronous;
+       status = "okay";
+};
+
 &spdif1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spdif1>;