arm64: dts: imx8mp-somdevices.dtsi: Configure WiFi/BT pins.

By default BT is not connected.

Signed-off-by: Josep Orga <jorga@somdevices.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi
index 89cbedf..e7ab5f6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-somdevices.dtsi
@@ -33,6 +33,15 @@
                reg = <0x0 0x40000000 0 0x80000000>;
        };
 
+       modem_reset: modem-reset {
+               compatible = "gpio-reset";
+               reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+               reset-delay-us = <2000>;
+               reset-post-delay-ms = <40>;
+               #reset-cells = <0>;
+               status = "disabled";
+       };
+
        reg_usdhc2_vmmc: regulator-usdhc2 {
                compatible = "regulator-fixed";
                pinctrl-names = "default";
@@ -69,7 +78,7 @@
                simple-audio-card,bitclock-master = <&btcpu>;
 
                btcpu: simple-audio-card,cpu {
-                       sound-dai = <&sai2>;
+                       sound-dai = <&sai5>;
                        dai-tdm-slot-num = <2>;
                        dai-tdm-slot-width = <16>;
                };
@@ -112,6 +121,14 @@
                                    100>;
                default-brightness-level = <80>;
        };
+
+       usdhc1_pwrseq: usdhc1_pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usdhc1_gpio>;
+               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>,
+                             <&gpio2 6 GPIO_ACTIVE_LOW>;
+       };
 };
 
 &A53_0 {
@@ -455,6 +472,22 @@
        status = "okay";
 };
 
+&sai5 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai5>;
+       assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
+       assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <24576000>;
+       clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG>, <&clk IMX8MP_CLK_DUMMY>,
+               <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
+               <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>,
+               <&clk IMX8MP_AUDIO_PLL2_OUT>;
+       clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
+       fsl,sai-asynchronous;
+       #sound-dai-cells = <0>;
+       status = "disabled";
+};
+
 &xcvr {
        #sound-dai-cells = <0>;
        status = "okay";
@@ -464,7 +497,7 @@
        status = "okay";
 };
 
-&uart1 { /* BT */
+&uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
        assigned-clocks = <&clk IMX8MP_CLK_UART1>;
@@ -523,6 +556,27 @@
        status = "okay";
 };
 
+&usdhc1 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+       bus-width = <4>;
+       cap-power-off-card;
+       pm-ignore-notify;
+       keep-power-in-suspend;
+       non-removable;
+       mmc-pwrseq = <&usdhc1_pwrseq>;
+       status = "okay";
+
+       wifi_wake_host {
+               compatible = "nxp,wifi-wake-host";
+               interrupt-parent = <&gpio2>;
+               interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "host-wake";
+       };
+};
+
 &usdhc2 {
        assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
        assigned-clock-rates = <400000000>;
@@ -713,12 +767,22 @@
                >;
        };
 
+       pinctrl_sai5: sai5grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00         0xd6
+                       MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC           0xd6
+                       MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK           0xd6
+                       MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00         0xd6
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x140
                        MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x140
                        MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS   0x140
                        MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS   0x140
+                       MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07      0x19
                >;
        };
 
@@ -744,6 +808,52 @@
                >;
        };
 
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK                0x190
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD                0x1d0
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0            0x1d0
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1            0x1d0
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2            0x1d0
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3            0x1d0
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09              0x1c4
+                       MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K     0x141
+               >;
+       };
+
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK                0x194
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD                0x1d4
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0            0x1d4
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1            0x1d4
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2            0x1d4
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3            0x1d4
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09              0x1c4
+                       MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K     0x141
+               >;
+       };
+
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK                0x196
+                       MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD                0x1d6
+                       MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0            0x1d6
+                       MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1            0x1d6
+                       MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2            0x1d6
+                       MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3            0x1d6
+                       MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09              0x1c4
+                       MX8MP_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K     0x141
+               >;
+       };
+
+       pinctrl_usdhc1_gpio: usdhc1grpgpio {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10    0x19
+                       MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x19
+               >;
+       };
+
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
                        MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190