arm64: dts: Change old UART4 pins:

	· Ethernet phy reset changed to SAI2_MCLK_GPIO4_IO27.
	· Pcie clkreq changed to I2C4_SCL_PCIE1_CLKREQ_B.

Signed-off-by: Josep Orga <jorga@somdevices.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
index a6d8da9..bc19efc 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-somdevices.dtsi
@@ -215,7 +215,7 @@
        pinctrl-0 = <&pinctrl_fec1>;
        phy-mode = "rgmii-id";
        phy-handle = <&ethphy0>;
-       phy-reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
+       phy-reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
        phy-reset-post-delay = <150>;
        phy-reset-duration = <10>;
        phy-reset-in-suspend;
@@ -751,7 +751,7 @@
                        MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
                        MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
                        MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
-                       MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29               0x19
+                       MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27               0x19
                >;
        };
 
@@ -801,7 +801,7 @@
 
        pinctrl_pcie0: pcie0grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B   0x61 /* open drain, pull up */
+                       MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61 /* open drain, pull up */
                        MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27       0x41
                        MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26       0x41
                >;