RDMA/hns: Add CQ flag instead of independent enable flag

It's easier to understand and maintain enable flags of cq using a single
field in type of u32 than defining a field for every flags in the
structure hns_roce_cq, and we can add new flags for features more
conveniently in the future.

Link: https://lore.kernel.org/r/1589982799-28728-3-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>

diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c
index 6dd8dea..e87d616 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_cq.c
+++ b/drivers/infiniband/hw/hns/hns_roce_cq.c
@@ -186,8 +186,8 @@ static int alloc_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
                                                   &hr_cq->db);
                        if (err)
                                return err;
-                       hr_cq->db_en = 1;
-                       resp->cap_flags |= HNS_ROCE_SUPPORT_CQ_RECORD_DB;
+                       hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
+                       resp->cap_flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
                }
        } else {
                if (has_db) {
@@ -196,7 +196,7 @@ static int alloc_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
                                return err;
                        hr_cq->set_ci_db = hr_cq->db.db_record;
                        *hr_cq->set_ci_db = 0;
-                       hr_cq->db_en = 1;
+                       hr_cq->flags |= HNS_ROCE_CQ_FLAG_RECORD_DB;
                }
                hr_cq->cq_db_l = hr_dev->reg_base + hr_dev->odb_offset +
                                 DB_REG_OFFSET * hr_dev->priv_uar.index;
@@ -210,10 +210,10 @@ static void free_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq,
 {
        struct hns_roce_ucontext *uctx;
 
-       if (!hr_cq->db_en)
+       if (!(hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB))
                return;
 
-       hr_cq->db_en = 0;
+       hr_cq->flags &= ~HNS_ROCE_CQ_FLAG_RECORD_DB;
        if (udata) {
                uctx = rdma_udata_to_drv_context(udata,
                                                 struct hns_roce_ucontext,

diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index bd6e295..f614959 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -137,8 +137,8 @@ enum {
        HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1),
 };
 
-enum {
-       HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0,
+enum hns_roce_cq_flags {
+       HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0),
 };
 
 enum hns_roce_qp_state {
@@ -458,7 +458,7 @@ struct hns_roce_cq {
        struct ib_cq                    ib_cq;
        struct hns_roce_mtr             mtr;
        struct hns_roce_db              db;
-       u8                              db_en;
+       u32                             flags;
        spinlock_t                      lock;
        u32                             cq_depth;
        u32                             cons_index;

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 6229b57..f002183 100644 (file)
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -2898,9 +2898,9 @@ static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
        roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
                       V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
 
-       if (hr_cq->db_en)
-               roce_set_bit(cq_context->byte_44_db_record,
-                            V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
+       roce_set_bit(cq_context->byte_44_db_record,
+                    V2_CQC_BYTE_44_DB_RECORD_EN_S,
+                    (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0);
 
        roce_set_field(cq_context->byte_44_db_record,
                       V2_CQC_BYTE_44_DB_RECORD_ADDR_M,