MLK-16155-3 mmc: host: Add CQE interface

Add CQE host operations, capabilities, and host members.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>

diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index aa85d57..726f932 100644 (file)
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -162,6 +162,19 @@ struct mmc_host_ops {
                                  unsigned int direction, int blk_size);
 };
 
+struct mmc_cqe_ops {
+       int     (*cqe_enable)(struct mmc_host *host, struct mmc_card *card);
+       void    (*cqe_disable)(struct mmc_host *host);
+       int     (*cqe_request)(struct mmc_host *host, struct mmc_request *mrq);
+       void    (*cqe_post_req)(struct mmc_host *host, struct mmc_request *mrq);
+       void    (*cqe_off)(struct mmc_host *host);
+       int     (*cqe_wait_for_idle)(struct mmc_host *host);
+       bool    (*cqe_timeout)(struct mmc_host *host, struct mmc_request *mrq,
+                              bool *recovery_needed);
+       void    (*cqe_recovery_start)(struct mmc_host *host);
+       void    (*cqe_recovery_finish)(struct mmc_host *host);
+};
+
 struct mmc_async_req {
        /* active mmc request */
        struct mmc_request      *mrq;
@@ -308,7 +321,8 @@ struct mmc_host {
 #define MMC_CAP2_NO_MMC                (1 << 22)       /* Do not send (e)MMC commands during initialization */
 #define MMC_CAP2_CD_POST       (1 << 23)       /* post card rescan, let client driver to start */
 #define MMC_CAP2_DDR52_3_3V    (1 << 24)       /* Only supprot eMMC DDR52 at 3.3v */
-
+#define MMC_CAP2_CQE           (1 << 25)       /* Has eMMC command queue engine */
+#define MMC_CAP2_CQE_DCMD      (1 << 26)       /* CQE can issue a direct command */
        mmc_pm_flag_t           pm_caps;        /* supported pm features */
 
        /* host specific block data */
@@ -394,6 +408,15 @@ struct mmc_host {
        int                     dsr_req;        /* DSR value is valid */
        u32                     dsr;    /* optional driver stage (DSR) value */
 
+       /* Command Queue Engine (CQE) support */
+       const struct mmc_cqe_ops *cqe_ops;
+       void                    *cqe_private;
+       void                    (*cqe_recovery_notifier)(struct mmc_host *,
+                                                        struct mmc_request *);
+       int                     cqe_qdepth;
+       bool                    cqe_enabled;
+       bool                    cqe_on;
+
        unsigned long           private[0] ____cacheline_aligned;
 };