MLK-11497-1 ARM: dts: add busfreq support for imx6q/dl
authorAnson Huang <b20788@freescale.com>
Sun, 6 Sep 2015 05:35:55 +0000 (13:35 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 19:48:25 +0000 (14:48 -0500)
Add busfreq support for i.MX6Q/DL.

Signed-off-by: Anson Huang <b20788@freescale.com>
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx6qdl.dtsi

index 08796e2..b29ba87 100644 (file)
        };
 
        soc {
+               busfreq {
+                       compatible = "fsl,imx_busfreq";
+                       clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                               <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>,
+                               <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>,
+                               <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>,
+                               <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>,
+                               <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> ,
+                               <&clks IMX6QDL_CLK_PLL3_PFD1_540M>;
+                       clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
+                               "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
+                       interrupts = <0 107 0x04>, <0 112 0x4>;
+                       interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
+                       fsl,max_ddr_freq = <400000000>;
+               };
+
                ocram: sram@00905000 {
                        compatible = "mmio-sram";
                        reg = <0x00905000 0x1B000>;
index 1eed65c..78313f1 100644 (file)
        };
 
        soc {
+               busfreq {
+                       compatible = "fsl,imx_busfreq";
+                       clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
+                               <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
+                       clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
+                               "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
+                       interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
+                       interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
+                       fsl,max_ddr_freq = <528000000>;
+               };
+
                ocram: sram@00905000 {
                        compatible = "mmio-sram";
                        reg = <0x00905000 0x3B000>;
index 780e21d..009ec6a 100644 (file)
                                reg = <0x021ac000 0x4000>;
                        };
 
+                       mmdc0-1@021b0000 { /* MMDC0-1 */
+                               compatible = "fsl,imx6q-mmdc-combine";
+                               reg = <0x021b0000 0x8000>;
+                       };
+
                        mmdc0: mmdc@021b0000 { /* MMDC0 */
                                compatible = "fsl,imx6q-mmdc";
                                reg = <0x021b0000 0x4000>;