#include "pcie-designware.h"
-#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
+#define to_imx_pcie(x) container_of(x, struct imx_pcie, pp)
-enum imx6_pcie_variants {
+enum imx_pcie_variants {
IMX6Q,
IMX6SX,
IMX6QP,
static u32 ddr_test_region = 0, test_region_size = SZ_2M;
static bool dma_w_end, dma_r_end, dma_en;
-struct imx6_pcie {
+struct imx_pcie {
struct pcie_port pp; /* pp.dbi_base is DT 0th resource */
u32 ext_osc;
u32 ctrl_id;
struct clk *pcie;
struct clk *pcie_ext_src;
struct regmap *iomuxc_gpr;
- enum imx6_pcie_variants variant;
+ enum imx_pcie_variants variant;
u32 hsio_cfg;
u32 tx_deemph_gen1;
u32 tx_deemph_gen2_3p5db;
#define IMX8MQ_GPC_PCG_PCIE_CTRL_PCR BIT(0)
#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
-static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
+static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, int exp_val)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
u32 val;
u32 max_iterations = 10;
u32 wait_counter = 0;
return -ETIMEDOUT;
}
-static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
+static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
u32 val;
int ret;
val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val);
- ret = pcie_phy_poll_ack(imx6_pcie, 1);
+ ret = pcie_phy_poll_ack(imx_pcie, 1);
if (ret)
return ret;
val = addr << PCIE_PHY_CTRL_DATA_LOC;
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val);
- return pcie_phy_poll_ack(imx6_pcie, 0);
+ return pcie_phy_poll_ack(imx_pcie, 0);
}
/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
-static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
+static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, int *data)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
u32 val, phy_ctl;
int ret;
- ret = pcie_phy_wait_ack(imx6_pcie, addr);
+ ret = pcie_phy_wait_ack(imx_pcie, addr);
if (ret)
return ret;
phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, phy_ctl);
- ret = pcie_phy_poll_ack(imx6_pcie, 1);
+ ret = pcie_phy_poll_ack(imx_pcie, 1);
if (ret)
return ret;
/* deassert Read signal */
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, 0x00);
- return pcie_phy_poll_ack(imx6_pcie, 0);
+ return pcie_phy_poll_ack(imx_pcie, 0);
}
-static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
+static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, int data)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
u32 var;
int ret;
/* write addr */
/* cap addr */
- ret = pcie_phy_wait_ack(imx6_pcie, addr);
+ ret = pcie_phy_wait_ack(imx_pcie, addr);
if (ret)
return ret;
var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
- ret = pcie_phy_poll_ack(imx6_pcie, 1);
+ ret = pcie_phy_poll_ack(imx_pcie, 1);
if (ret)
return ret;
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
- ret = pcie_phy_poll_ack(imx6_pcie, 0);
+ ret = pcie_phy_poll_ack(imx_pcie, 0);
if (ret)
return ret;
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
/* wait for ack */
- ret = pcie_phy_poll_ack(imx6_pcie, 1);
+ ret = pcie_phy_poll_ack(imx_pcie, 1);
if (ret)
return ret;
dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var);
/* wait for ack de-assertion */
- ret = pcie_phy_poll_ack(imx6_pcie, 0);
+ ret = pcie_phy_poll_ack(imx_pcie, 0);
if (ret)
return ret;
return 0;
}
-static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie)
{
u32 tmp;
- if (imx6_pcie->variant == IMX6Q || imx6_pcie->variant == IMX6SX
- || imx6_pcie->variant == IMX6QP) {
- pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
+ if (imx_pcie->variant == IMX6Q || imx_pcie->variant == IMX6SX
+ || imx_pcie->variant == IMX6QP) {
+ pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
- pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
+ pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
usleep_range(2000, 3000);
- pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
+ pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp);
tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
- pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
+ pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp);
}
}
#ifdef CONFIG_ARM
/* Added for PCI abort handling */
-static int imx6q_pcie_abort_handler(unsigned long addr,
+static int imx_pcie_abort_handler(unsigned long addr,
unsigned int fsr, struct pt_regs *regs)
{
return 0;
}
#endif
-static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
u32 val, gpr1, gpr12;
int i;
- switch (imx6_pcie->variant) {
+ switch (imx_pcie->variant) {
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
/* Force PCIe PHY reset */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET,
IMX6SX_GPR5_PCIE_BTNRST_RESET);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST,
IMX6Q_GPR1_PCIE_SW_RST);
break;
* have a strong indication that the bootloader activated
* the link.
*/
- regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
- regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
+ regmap_read(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
+ regmap_read(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
val |= PCIE_PL_PFLR_FORCE_LINK;
dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
}
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
break;
case IMX7D:
/* G_RST */
- regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(1), BIT(1));
+ regmap_update_bits(imx_pcie->reg_src, 0x2c, BIT(1), BIT(1));
/* BTNRST */
- regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), BIT(2));
+ regmap_update_bits(imx_pcie->reg_src, 0x2c, BIT(2), BIT(2));
break;
case IMX8QXP:
val = IMX8QM_CSR_PCIEB_OFFSET;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_BUTTON_RST_N,
IMX8QM_CTRL_BUTTON_RST_N);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_PERST_N,
IMX8QM_CTRL_PERST_N);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_POWER_UP_RST_N,
IMX8QM_CTRL_POWER_UP_RST_N);
break;
case IMX8QM:
- for (i = 0; i <= imx6_pcie->ctrl_id; i++) {
+ for (i = 0; i <= imx_pcie->ctrl_id; i++) {
val = IMX8QM_CSR_PCIEA_OFFSET + i * SZ_64K;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_BUTTON_RST_N,
IMX8QM_CTRL_BUTTON_RST_N);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_PERST_N,
IMX8QM_CTRL_PERST_N);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_POWER_UP_RST_N,
IMX8QM_CTRL_POWER_UP_RST_N);
}
break;
case IMX8MQ:
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
val = IMX8MQ_SRC_PCIEPHY_RCR_OFFSET;
else
val = IMX8MQ_SRC_PCIE2PHY_RCR_OFFSET;
/* Do RSTs */
- regmap_update_bits(imx6_pcie->reg_src, val,
+ regmap_update_bits(imx_pcie->reg_src, val,
IMX8MQ_PCIEPHY_BTN,
IMX8MQ_PCIEPHY_BTN);
- regmap_update_bits(imx6_pcie->reg_src, val,
+ regmap_update_bits(imx_pcie->reg_src, val,
IMX8MQ_PCIEPHY_G_RST,
IMX8MQ_PCIEPHY_G_RST);
}
}
-static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
int ret = 0;
- switch (imx6_pcie->variant) {
+ switch (imx_pcie->variant) {
case IMX6SX:
- ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+ ret = clk_prepare_enable(imx_pcie->pcie_inbound_axi);
if (ret) {
dev_err(dev, "unable to enable pcie_axi clock\n");
break;
}
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
break;
case IMX6QP: /* FALLTHROUGH */
case IMX6Q:
/* power up core phy and enable ref clock */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
/*
* the async reset input need ref clock to sync internally,
* add one ~10us delay here.
*/
udelay(10);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
break;
case IMX7D:
break;
case IMX8QXP:
case IMX8QM:
- ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+ ret = clk_prepare_enable(imx_pcie->pcie_inbound_axi);
if (ret) {
dev_err(dev, "unable to enable pcie_axi clock\n");
break;
}
- ret = clk_prepare_enable(imx6_pcie->pcie_per);
+ ret = clk_prepare_enable(imx_pcie->pcie_per);
if (ret) {
dev_err(dev, "unable to enable pcie_per clock\n");
- clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
+ clk_disable_unprepare(imx_pcie->pcie_inbound_axi);
break;
}
return ret;
}
-static int pci_imx_phy_pll_locked(struct imx6_pcie *imx6_pcie)
+static int pci_imx_phy_pll_locked(struct imx_pcie *imx_pcie)
{
u32 val, tmp, orig;
int i = 0;
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
- if (imx6_pcie->variant == IMX7D) {
+ if (imx_pcie->variant == IMX7D) {
for (i = 0; i < 100; i++) {
- regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &tmp);
+ regmap_read(imx_pcie->iomuxc_gpr, IOMUXC_GPR22, &tmp);
if (tmp & BIT(31))
break;
udelay(10);
}
- } else if (imx6_pcie->variant == IMX8QXP
- || imx6_pcie->variant == IMX8QM) {
+ } else if (imx_pcie->variant == IMX8QXP
+ || imx_pcie->variant == IMX8QM) {
for (i = 0; i < 100; i++) {
- if (imx6_pcie->hsio_cfg == PCIEAX2SATA) {
- regmap_read(imx6_pcie->iomuxc_gpr,
+ if (imx_pcie->hsio_cfg == PCIEAX2SATA) {
+ regmap_read(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_PHYX2_OFFSET + 0x4,
&tmp);
orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
tmp &= orig;
if (tmp == orig) {
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_LPCG_PHYX2_OFFSET,
IMX8QM_LPCG_PHY_PCG0
| IMX8QM_LPCG_PHY_PCG1,
}
}
- if (imx6_pcie->hsio_cfg == PCIEAX1PCIEBX1SATA) {
- regmap_read(imx6_pcie->iomuxc_gpr,
+ if (imx_pcie->hsio_cfg == PCIEAX1PCIEBX1SATA) {
+ regmap_read(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_PHYX2_OFFSET + 0x4,
&tmp);
- if (imx6_pcie->ctrl_id == 0) /* pciea 1 lanes */
+ if (imx_pcie->ctrl_id == 0) /* pciea 1 lanes */
orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
else /* pcieb 1 lanes */
orig = IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
tmp &= orig;
if (tmp == orig) {
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_LPCG_PHYX2_OFFSET,
IMX8QM_LPCG_PHY_PCG0
| IMX8QM_LPCG_PHY_PCG1,
}
}
- if (imx6_pcie->hsio_cfg == PCIEAX2PCIEBX1) {
+ if (imx_pcie->hsio_cfg == PCIEAX2PCIEBX1) {
val = IMX8QM_CSR_PHYX2_OFFSET
- + imx6_pcie->ctrl_id * SZ_64K;
- regmap_read(imx6_pcie->iomuxc_gpr,
+ + imx_pcie->ctrl_id * SZ_64K;
+ regmap_read(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PHYX_STTS0_OFFSET,
&tmp);
orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
- if (imx6_pcie->ctrl_id == 0) /* pciea 2 lanes */
+ if (imx_pcie->ctrl_id == 0) /* pciea 2 lanes */
orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
tmp &= orig;
if (tmp == orig) {
val = IMX8QM_CSR_PHYX2_OFFSET
- + imx6_pcie->ctrl_id * SZ_64K;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ + imx_pcie->ctrl_id * SZ_64K;
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val, IMX8QM_LPCG_PHY_PCG0,
IMX8QM_LPCG_PHY_PCG0);
break;
}
}
-static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
int ret, i;
u32 val, tmp;
- if (gpio_is_valid(imx6_pcie->power_on_gpio))
- gpio_set_value_cansleep(imx6_pcie->power_on_gpio, 1);
+ if (gpio_is_valid(imx_pcie->power_on_gpio))
+ gpio_set_value_cansleep(imx_pcie->power_on_gpio, 1);
- ret = clk_prepare_enable(imx6_pcie->pcie);
+ ret = clk_prepare_enable(imx_pcie->pcie);
if (ret) {
dev_err(dev, "unable to enable pcie clock\n");
return -ENODEV;
}
- if (imx6_pcie->ext_osc && (imx6_pcie->variant == IMX6QP))
- clk_set_parent(imx6_pcie->pcie_bus,
- imx6_pcie->pcie_ext_src);
- ret = clk_prepare_enable(imx6_pcie->pcie_bus);
+ if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP))
+ clk_set_parent(imx_pcie->pcie_bus,
+ imx_pcie->pcie_ext_src);
+ ret = clk_prepare_enable(imx_pcie->pcie_bus);
if (ret) {
dev_err(pp->dev, "unable to enable pcie_bus clock\n");
goto err_pcie_bus;
}
- ret = clk_prepare_enable(imx6_pcie->pcie_phy);
+ ret = clk_prepare_enable(imx_pcie->pcie_phy);
if (ret) {
dev_err(dev, "unable to enable pcie_phy clock\n");
goto err_pcie_phy;
}
- ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+ ret = imx_pcie_enable_ref_clk(imx_pcie);
if (ret) {
dev_err(dev, "unable to enable pcie ref clock\n");
goto err_ref_clk;
/* allow the clocks to stabilize */
udelay(200);
- switch (imx6_pcie->variant) {
+ switch (imx_pcie->variant) {
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST, 0);
udelay(200);
/* Configure the PHY when 100Mhz external OSC is used as input clock */
- if (!imx6_pcie->ext_osc)
+ if (!imx_pcie->ext_osc)
break;
mdelay(4);
- pcie_phy_read(imx6_pcie, SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO, &val);
+ pcie_phy_read(imx_pcie, SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO, &val);
/* MPLL_MULTIPLIER [8:2] */
val &= ~(0x7F << 2);
val |= (0x19 << 2);
/* MPLL_MULTIPLIER_OVRD [9:9] */
val |= (0x1 << 9);
- pcie_phy_write(imx6_pcie, SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO, val);
+ pcie_phy_write(imx_pcie, SSP_CR_SUP_DIG_MPLL_OVRD_IN_LO, val);
mdelay(4);
- pcie_phy_read(imx6_pcie, SSP_CR_SUP_DIG_ATEOVRD, &val);
+ pcie_phy_read(imx_pcie, SSP_CR_SUP_DIG_ATEOVRD, &val);
/* ref_clkdiv2 [0:0] */
val &= ~0x1;
/* ateovrd_en [2:2] */
val |= 0x4;
- pcie_phy_write(imx6_pcie, SSP_CR_SUP_DIG_ATEOVRD, val);
+ pcie_phy_write(imx_pcie, SSP_CR_SUP_DIG_ATEOVRD, val);
mdelay(4);
break;
case IMX6Q:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST, 0);
/*
* some delay are required by 6qp, after the SW_RST is
case IMX7D:
/* wait for more than 10us to release phy g_rst and btnrst */
udelay(10);
- regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(6), 0);
- regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(1), 0);
+ regmap_update_bits(imx_pcie->reg_src, 0x2c, BIT(6), 0);
+ regmap_update_bits(imx_pcie->reg_src, 0x2c, BIT(1), 0);
/* Add the workaround for ERR010728 */
- if (unlikely(imx6_pcie->phy_base == NULL)) {
+ if (unlikely(imx_pcie->phy_base == NULL)) {
dev_err(dev, "phy base shouldn't be null.\n");
} else {
/* De-assert DCC_FB_EN by writing data "0x29". */
writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
/* Assert RX_EQS and RX_EQS_SEL */
writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
| PCIE_PHY_CMN_REG24_RX_EQ,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
/* Assert ATT_MODE by writing data "0xBC". */
writel(PCIE_PHY_CMN_REG26_ATT_MODE,
- imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
}
- regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), 0);
+ regmap_update_bits(imx_pcie->reg_src, 0x2c, BIT(2), 0);
/* wait for phy pll lock firstly. */
- if (pci_imx_phy_pll_locked(imx6_pcie))
+ if (pci_imx_phy_pll_locked(imx_pcie))
ret = -ENODEV;
break;
case IMX8QXP:
/* bit19 PM_REQ_CORE_RST of pciex#_stts0 should be cleared. */
for (i = 0; i < 100; i++) {
val = IMX8QM_CSR_PCIEA_OFFSET
- + imx6_pcie->ctrl_id * SZ_64K;
- regmap_read(imx6_pcie->iomuxc_gpr,
+ + imx_pcie->ctrl_id * SZ_64K;
+ regmap_read(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_STTS0_OFFSET,
&tmp);
if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) == 0)
dev_err(dev, "ERROR PM_REQ_CORE_RST is still set.\n");
/* wait for phy pll lock firstly. */
- if (pci_imx_phy_pll_locked(imx6_pcie)) {
+ if (pci_imx_phy_pll_locked(imx_pcie)) {
ret = -ENODEV;
break;
}
/* set up the cpu address offset */
- if (imx6_pcie->cpu_base)
- pp->cpu_addr_offset = imx6_pcie->cpu_base
+ if (imx_pcie->cpu_base)
+ pp->cpu_addr_offset = imx_pcie->cpu_base
- pp->mem_base;
else
pp->cpu_addr_offset = 0;
case IMX8MQ:
/* wait for more than 10us to release phy g_rst and btnrst */
udelay(10);
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
val = IMX8MQ_SRC_PCIEPHY_RCR_OFFSET;
else
val = IMX8MQ_SRC_PCIE2PHY_RCR_OFFSET;
- regmap_update_bits(imx6_pcie->reg_src, val,
+ regmap_update_bits(imx_pcie->reg_src, val,
IMX8MQ_PCIEPHY_BTN, 0);
- regmap_update_bits(imx6_pcie->reg_src, val,
+ regmap_update_bits(imx_pcie->reg_src, val,
IMX8MQ_PCIEPHY_G_RST, 0);
- regmap_update_bits(imx6_pcie->reg_src, val,
+ regmap_update_bits(imx_pcie->reg_src, val,
IMX8MQ_PCIE_CTRL_APPS_EN, 0);
break;
}
/* Some boards don't have PCIe reset GPIO. */
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high);
+ if (gpio_is_valid(imx_pcie->reset_gpio)) {
+ gpio_set_value_cansleep(imx_pcie->reset_gpio,
+ imx_pcie->gpio_active_high);
mdelay(20);
- gpio_set_value_cansleep(imx6_pcie->reset_gpio,
- !imx6_pcie->gpio_active_high);
+ gpio_set_value_cansleep(imx_pcie->reset_gpio,
+ !imx_pcie->gpio_active_high);
mdelay(20);
}
return ret;
err_ref_clk:
- clk_disable_unprepare(imx6_pcie->pcie_phy);
+ clk_disable_unprepare(imx_pcie->pcie_phy);
err_pcie_phy:
- clk_disable_unprepare(imx6_pcie->pcie_bus);
+ clk_disable_unprepare(imx_pcie->pcie_bus);
err_pcie_bus:
- clk_disable_unprepare(imx6_pcie->pcie);
+ clk_disable_unprepare(imx_pcie->pcie);
return ret;
}
-static void imx6_pcie_phy_pwr_up(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_phy_pwr_up(struct imx_pcie *imx_pcie)
{
u32 val, offset;
unsigned long timeout = jiffies + msecs_to_jiffies(500);
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
- if (imx6_pcie->variant != IMX8MQ)
+ if (imx_pcie->variant != IMX8MQ)
return;
/*
* Power up PHY.
* 1? external osc : internal pll
*/
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
offset = 0;
else
offset = IMX8MQ_GPC_PGC_PCIE2_BIT_OFFSET;
- regmap_update_bits(imx6_pcie->reg_gpc,
+ regmap_update_bits(imx_pcie->reg_gpc,
IMX8MQ_GPC_PGC_CPU_0_1_MAPPING_OFFSET,
IMX8MQ_GPC_PGC_PCIE_A53_DOMAIN << offset,
IMX8MQ_GPC_PGC_PCIE_A53_DOMAIN << offset);
- regmap_update_bits(imx6_pcie->reg_gpc,
+ regmap_update_bits(imx_pcie->reg_gpc,
IMX8MQ_GPC_PU_PGC_SW_PUP_REQ_OFFSET,
IMX8MQ_GPC_PU_PGC_PCIE_SW_PWR_REQ << offset,
IMX8MQ_GPC_PU_PGC_PCIE_SW_PWR_REQ << offset);
- regmap_read(imx6_pcie->reg_gpc,
+ regmap_read(imx_pcie->reg_gpc,
IMX8MQ_GPC_PU_PGC_SW_PUP_REQ_OFFSET,
&val);
while (val & (IMX8MQ_GPC_PU_PGC_PCIE_SW_PWR_REQ << offset)) {
- regmap_read(imx6_pcie->reg_gpc,
+ regmap_read(imx_pcie->reg_gpc,
IMX8MQ_GPC_PU_PGC_SW_PUP_REQ_OFFSET,
&val);
if (time_after(jiffies, timeout)) {
dev_err(dev, "CAN NOT PWR UP PCIE%d PHY!\n",
- imx6_pcie->ctrl_id);
+ imx_pcie->ctrl_id);
break;
}
}
udelay(1);
}
-static void imx6_pcie_phy_pwr_dn(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_phy_pwr_dn(struct imx_pcie *imx_pcie)
{
u32 val, offset;
unsigned long timeout = jiffies + msecs_to_jiffies(500);
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
- if (imx6_pcie->variant != IMX8MQ)
+ if (imx_pcie->variant != IMX8MQ)
return;
/*
* Power up PHY.
* 1? external osc : internal pll
*/
- if (imx6_pcie->ctrl_id == 0) {
+ if (imx_pcie->ctrl_id == 0) {
offset = 0;
- regmap_update_bits(imx6_pcie->reg_gpc,
+ regmap_update_bits(imx_pcie->reg_gpc,
IMX8MQ_GPC_PGC_PCIE_CTRL_OFFSET,
IMX8MQ_GPC_PCG_PCIE_CTRL_PCR,
IMX8MQ_GPC_PCG_PCIE_CTRL_PCR);
} else {
offset = IMX8MQ_GPC_PGC_PCIE2_BIT_OFFSET;
- regmap_update_bits(imx6_pcie->reg_gpc,
+ regmap_update_bits(imx_pcie->reg_gpc,
IMX8MQ_GPC_PGC_PCIE2_CTRL_OFFSET,
IMX8MQ_GPC_PCG_PCIE_CTRL_PCR,
IMX8MQ_GPC_PCG_PCIE_CTRL_PCR);
}
- regmap_update_bits(imx6_pcie->reg_gpc,
+ regmap_update_bits(imx_pcie->reg_gpc,
IMX8MQ_GPC_PGC_CPU_0_1_MAPPING_OFFSET,
IMX8MQ_GPC_PGC_PCIE_A53_DOMAIN << offset,
IMX8MQ_GPC_PGC_PCIE_A53_DOMAIN << offset);
- regmap_update_bits(imx6_pcie->reg_gpc,
+ regmap_update_bits(imx_pcie->reg_gpc,
IMX8MQ_GPC_PU_PGC_SW_PDN_REQ_OFFSET,
IMX8MQ_GPC_PU_PGC_PCIE_SW_PWR_REQ << offset,
IMX8MQ_GPC_PU_PGC_PCIE_SW_PWR_REQ << offset);
- regmap_read(imx6_pcie->reg_gpc,
+ regmap_read(imx_pcie->reg_gpc,
IMX8MQ_GPC_PU_PGC_SW_PDN_REQ_OFFSET,
&val);
while (val & (IMX8MQ_GPC_PU_PGC_PCIE_SW_PWR_REQ << offset)) {
- regmap_read(imx6_pcie->reg_gpc,
+ regmap_read(imx_pcie->reg_gpc,
IMX8MQ_GPC_PU_PGC_SW_PDN_REQ_OFFSET,
&val);
if (time_after(jiffies, timeout)) {
dev_err(dev, "CAN NOT PWR DN PCIE%d PHY!\n",
- imx6_pcie->ctrl_id);
+ imx_pcie->ctrl_id);
break;
}
}
udelay(1);
}
-static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
+static void imx_pcie_init_phy(struct imx_pcie *imx_pcie)
{
u32 tmp, val;
int ret;
- if (imx6_pcie->variant == IMX8QM
- || imx6_pcie->variant == IMX8QXP) {
- switch (imx6_pcie->hsio_cfg) {
+ if (imx_pcie->variant == IMX8QM
+ || imx_pcie->variant == IMX8QXP) {
+ switch (imx_pcie->hsio_cfg) {
case PCIEAX2SATA:
/*
* bit 0 rx ena 1.
* bit12 PHY_X1_EPCS_SEL 1.
* bit13 phy_ab_select 0.
*/
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_PHYX2_OFFSET,
IMX8QM_PHYX2_CTRL0_APB_MASK,
IMX8QM_PHY_APB_RSTN_0
| IMX8QM_PHY_APB_RSTN_1);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_PHYX1_EPCS_SEL,
IMX8QM_MISC_PHYX1_EPCS_SEL);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_PCIE_AB_SELECT,
0);
case PCIEAX1PCIEBX1SATA:
tmp = IMX8QM_PHY_APB_RSTN_1;
tmp |= IMX8QM_PHY_APB_RSTN_0;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_PHYX2_OFFSET,
IMX8QM_PHYX2_CTRL0_APB_MASK, tmp);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_PHYX1_EPCS_SEL,
IMX8QM_MISC_PHYX1_EPCS_SEL);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_PCIE_AB_SELECT,
IMX8QM_MISC_PCIE_AB_SELECT);
* bit12 PHY_X1_EPCS_SEL 0.
* bit13 phy_ab_select 1.
*/
- if (imx6_pcie->ctrl_id)
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ if (imx_pcie->ctrl_id)
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_PHYX1_OFFSET,
IMX8QM_PHY_APB_RSTN_0,
IMX8QM_PHY_APB_RSTN_0);
else
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_PHYX2_OFFSET,
IMX8QM_PHYX2_CTRL0_APB_MASK,
IMX8QM_PHY_APB_RSTN_0
| IMX8QM_PHY_APB_RSTN_1);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_PHYX1_EPCS_SEL,
0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_PCIE_AB_SELECT,
IMX8QM_MISC_PCIE_AB_SELECT);
break;
}
- if (imx6_pcie->ext_osc) {
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ if (imx_pcie->ext_osc) {
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_IOB_RXENA,
IMX8QM_MISC_IOB_RXENA);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_IOB_TXENA,
0);
} else {
/* Try to used the internal pll as ref clk */
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_IOB_RXENA,
0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_MISC_IOB_TXENA,
IMX8QM_MISC_IOB_TXENA);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IMX8QM_CSR_MISC_OFFSET,
IMX8QM_CSR_MISC_IOB_A_0_TXOE
| IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK,
IMX8QM_CSR_MISC_IOB_A_0_TXOE
| IMX8QM_CSR_MISC_IOB_A_0_M1M0_2);
}
- } else if (imx6_pcie->variant == IMX8MQ) {
- imx6_pcie_phy_pwr_up(imx6_pcie);
+ } else if (imx_pcie->variant == IMX8MQ) {
+ imx_pcie_phy_pwr_up(imx_pcie);
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
val = IOMUXC_GPR14;
else
val = IOMUXC_GPR16;
- regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, val,
IMX8MQ_GPR_PCIE_REF_USE_PAD,
IMX8MQ_GPR_PCIE_REF_USE_PAD);
- } else if (imx6_pcie->variant == IMX7D) {
+ } else if (imx_pcie->variant == IMX7D) {
/* Enable PCIe PHY 1P0D */
- regulator_set_voltage(imx6_pcie->pcie_phy_regulator,
+ regulator_set_voltage(imx_pcie->pcie_phy_regulator,
1000000, 1000000);
- ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
+ ret = regulator_enable(imx_pcie->pcie_phy_regulator);
if (ret)
- dev_err(imx6_pcie->pp.dev,
+ dev_err(imx_pcie->pp.dev,
"failed to enable pcie regulator\n");
/* pcie phy ref clock select; 1? internal pll : external osc */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
BIT(5), 0);
- } else if (imx6_pcie->variant == IMX6SX) {
+ } else if (imx_pcie->variant == IMX6SX) {
/* Force PCIe PHY reset */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET,
IMX6SX_GPR5_PCIE_BTNRST_RESET);
- regulator_set_voltage(imx6_pcie->pcie_phy_regulator,
+ regulator_set_voltage(imx_pcie->pcie_phy_regulator,
1100000, 1100000);
- ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
+ ret = regulator_enable(imx_pcie->pcie_phy_regulator);
if (ret)
- dev_err(imx6_pcie->pp.dev,
+ dev_err(imx_pcie->pp.dev,
"failed to enable pcie regulator.\n");
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_RX_EQ_MASK,
IMX6SX_GPR12_PCIE_RX_EQ_2);
}
- if (imx6_pcie->pcie_bus_regulator != NULL) {
- ret = regulator_enable(imx6_pcie->pcie_bus_regulator);
+ if (imx_pcie->pcie_bus_regulator != NULL) {
+ ret = regulator_enable(imx_pcie->pcie_bus_regulator);
if (ret)
- dev_err(imx6_pcie->pp.dev, "failed to enable pcie regulator.\n");
+ dev_err(imx_pcie->pp.dev, "failed to enable pcie regulator.\n");
}
- if ((imx6_pcie->variant == IMX6Q) || (imx6_pcie->variant == IMX6QP)
- || (imx6_pcie->variant == IMX6SX)) {
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ if ((imx_pcie->variant == IMX6Q) || (imx_pcie->variant == IMX6QP)
+ || (imx_pcie->variant == IMX6SX)) {
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
/* configure constant input signal to the pcie ctrl and phy */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_LOS_LEVEL, IMX6Q_GPR12_LOS_LEVEL_9);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN1,
- imx6_pcie->tx_deemph_gen1 << 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen1 << 0);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
- imx6_pcie->tx_deemph_gen2_3p5db << 6);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen2_3p5db << 6);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
- imx6_pcie->tx_deemph_gen2_6db << 12);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_deemph_gen2_6db << 12);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_SWING_FULL,
- imx6_pcie->tx_swing_full << 18);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ imx_pcie->tx_swing_full << 18);
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8,
IMX6Q_GPR8_TX_SWING_LOW,
- imx6_pcie->tx_swing_low << 25);
+ imx_pcie->tx_swing_low << 25);
}
/* configure the device type */
if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
- if (imx6_pcie->variant == IMX8QM
- || imx6_pcie->variant == IMX8QXP) {
+ if (imx_pcie->variant == IMX8QM
+ || imx_pcie->variant == IMX8QXP) {
val = IMX8QM_CSR_PCIEA_OFFSET
- + imx6_pcie->ctrl_id * SZ_64K;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ + imx_pcie->ctrl_id * SZ_64K;
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val, IMX8QM_PCIE_TYPE_MASK,
PCI_EXP_TYPE_ENDPOINT << 24);
} else {
- if (unlikely(imx6_pcie->ctrl_id))
+ if (unlikely(imx_pcie->ctrl_id))
/* iMX8MQ second PCIE */
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IOMUXC_GPR12,
IMX6Q_GPR12_DEVICE_TYPE >> 4,
PCI_EXP_TYPE_ENDPOINT << 8);
else
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IOMUXC_GPR12,
IMX6Q_GPR12_DEVICE_TYPE,
PCI_EXP_TYPE_ENDPOINT << 12);
}
} else {
- if (imx6_pcie->variant == IMX8QM
- || imx6_pcie->variant == IMX8QXP) {
+ if (imx_pcie->variant == IMX8QM
+ || imx_pcie->variant == IMX8QXP) {
val = IMX8QM_CSR_PCIEA_OFFSET
- + imx6_pcie->ctrl_id * SZ_64K;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ + imx_pcie->ctrl_id * SZ_64K;
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val, IMX8QM_PCIE_TYPE_MASK,
PCI_EXP_TYPE_ROOT_PORT << 24);
} else {
- if (unlikely(imx6_pcie->ctrl_id))
+ if (unlikely(imx_pcie->ctrl_id))
/* iMX8MQ second PCIE */
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IOMUXC_GPR12,
IMX6Q_GPR12_DEVICE_TYPE >> 4,
PCI_EXP_TYPE_ROOT_PORT << 8);
else
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
IOMUXC_GPR12,
IMX6Q_GPR12_DEVICE_TYPE,
PCI_EXP_TYPE_ROOT_PORT << 12);
}
}
-static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_wait_for_link(struct imx_pcie *imx_pcie)
{
int count = 20000;
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
/* check if the link is up or not */
return 0;
}
-static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
u32 tmp;
unsigned int retries;
return -EINVAL;
}
-static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
+static irqreturn_t imx_pcie_msi_handler(int irq, void *arg)
{
- struct imx6_pcie *imx6_pcie = arg;
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct imx_pcie *imx_pcie = arg;
+ struct pcie_port *pp = &imx_pcie->pp;
return dw_handle_msi_irq(pp);
}
static void pci_imx_clk_disable(struct device *dev)
{
u32 val;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
- clk_disable_unprepare(imx6_pcie->pcie);
- clk_disable_unprepare(imx6_pcie->pcie_phy);
- clk_disable_unprepare(imx6_pcie->pcie_bus);
- switch (imx6_pcie->variant) {
+ clk_disable_unprepare(imx_pcie->pcie);
+ clk_disable_unprepare(imx_pcie->pcie_phy);
+ clk_disable_unprepare(imx_pcie->pcie_bus);
+ switch (imx_pcie->variant) {
case IMX6Q:
break;
case IMX6SX:
- clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
+ clk_disable_unprepare(imx_pcie->pcie_inbound_axi);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD,
IMX6Q_GPR1_PCIE_TEST_PD);
break;
case IMX7D:
/* turn off external osc input */
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
BIT(5), BIT(5));
break;
case IMX8MQ:
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
val = IOMUXC_GPR14;
else
val = IOMUXC_GPR16;
- regmap_update_bits(imx6_pcie->iomuxc_gpr, val,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, val,
IMX8MQ_GPR_PCIE_REF_USE_PAD, 0);
break;
case IMX8QXP:
case IMX8QM:
- clk_disable_unprepare(imx6_pcie->pcie_per);
- clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
+ clk_disable_unprepare(imx_pcie->pcie_per);
+ clk_disable_unprepare(imx_pcie->pcie_inbound_axi);
break;
}
}
static void pci_imx_ltssm_enable(struct device *dev)
{
u32 val;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
- switch (imx6_pcie->variant) {
+ switch (imx_pcie->variant) {
case IMX6Q:
case IMX6SX:
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2,
IMX6Q_GPR12_PCIE_CTL_2);
break;
case IMX7D:
case IMX8MQ:
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
val = IMX8MQ_SRC_PCIEPHY_RCR_OFFSET;
else
val = IMX8MQ_SRC_PCIE2PHY_RCR_OFFSET;
- regmap_update_bits(imx6_pcie->reg_src, val,
+ regmap_update_bits(imx_pcie->reg_src, val,
IMX8MQ_PCIE_CTRL_APPS_EN,
IMX8MQ_PCIE_CTRL_APPS_EN);
break;
case IMX8QM:
/* Bit4 of the CTRL2 */
val = IMX8QM_CSR_PCIEA_OFFSET
- + imx6_pcie->ctrl_id * SZ_64K;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ + imx_pcie->ctrl_id * SZ_64K;
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_LTSSM_ENABLE,
IMX8QM_CTRL_LTSSM_ENABLE);
}
-static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
+static int imx_pcie_establish_link(struct imx_pcie *imx_pcie)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
u32 tmp;
int ret;
/* Start LTSSM. */
pci_imx_ltssm_enable(dev);
- ret = imx6_pcie_wait_for_link(imx6_pcie);
+ ret = imx_pcie_wait_for_link(imx_pcie);
if (ret) {
dev_info(dev, "Link never came up\n");
goto err_reset_phy;
}
- if (imx6_pcie->link_gen >= 2) {
+ if (imx_pcie->link_gen >= 2) {
/* Allow Gen2 mode after the link is up. */
tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCR);
tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
- tmp |= imx6_pcie->link_gen;
+ tmp |= imx_pcie->link_gen;
dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp);
} else {
dev_info(dev, "Link: Gen2 disabled\n");
tmp |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_writel_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
- ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
+ ret = imx_pcie_wait_for_speed_change(imx_pcie);
if (ret) {
dev_info(dev, "Roll back to GEN1 link!\n");
}
/* Make sure link training is finished as well! */
- ret = imx6_pcie_wait_for_link(imx6_pcie);
+ ret = imx_pcie_wait_for_link(imx_pcie);
if (ret) {
dev_err(dev, "Failed to bring link up!\n");
goto err_reset_phy;
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0),
dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1));
- imx6_pcie_reset_phy(imx6_pcie);
+ imx_pcie_reset_phy(imx_pcie);
if (!IS_ENABLED(CONFIG_PCI_IMX6_COMPLIANCE_TEST)) {
pci_imx_clk_disable(dev);
- if ((imx6_pcie->variant == IMX7D)
- || (imx6_pcie->variant == IMX8MQ)
- || (imx6_pcie->variant == IMX8QM)
- || (imx6_pcie->variant == IMX8QXP))
+ if ((imx_pcie->variant == IMX7D)
+ || (imx_pcie->variant == IMX8MQ)
+ || (imx_pcie->variant == IMX8QM)
+ || (imx_pcie->variant == IMX8QXP))
pm_runtime_put_sync(pp->dev);
- if (imx6_pcie->variant == IMX8MQ)
- imx6_pcie_phy_pwr_dn(imx6_pcie);
- if (imx6_pcie->pcie_phy_regulator != NULL)
- regulator_disable(imx6_pcie->pcie_phy_regulator);
- if (imx6_pcie->pcie_bus_regulator != NULL)
- regulator_disable(imx6_pcie->pcie_bus_regulator);
+ if (imx_pcie->variant == IMX8MQ)
+ imx_pcie_phy_pwr_dn(imx_pcie);
+ if (imx_pcie->pcie_phy_regulator != NULL)
+ regulator_disable(imx_pcie->pcie_phy_regulator);
+ if (imx_pcie->pcie_bus_regulator != NULL)
+ regulator_disable(imx_pcie->pcie_bus_regulator);
}
return ret;
}
-static int imx6_pcie_host_init(struct pcie_port *pp)
+static int imx_pcie_host_init(struct pcie_port *pp)
{
int ret;
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pp);
/* enable disp_mix power domain */
- if ((imx6_pcie->variant == IMX7D)
- || (imx6_pcie->variant == IMX8MQ)
- || (imx6_pcie->variant == IMX8QM)
- || (imx6_pcie->variant == IMX8QXP))
+ if ((imx_pcie->variant == IMX7D)
+ || (imx_pcie->variant == IMX8MQ)
+ || (imx_pcie->variant == IMX8QM)
+ || (imx_pcie->variant == IMX8QXP))
pm_runtime_get_sync(pp->dev);
- imx6_pcie_assert_core_reset(imx6_pcie);
- imx6_pcie_init_phy(imx6_pcie);
- ret = imx6_pcie_deassert_core_reset(imx6_pcie);
+ imx_pcie_assert_core_reset(imx_pcie);
+ imx_pcie_init_phy(imx_pcie);
+ ret = imx_pcie_deassert_core_reset(imx_pcie);
if (ret < 0)
return ret;
if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
dw_pcie_setup_rc(pp);
- ret = imx6_pcie_establish_link(imx6_pcie);
+ ret = imx_pcie_establish_link(imx_pcie);
if (ret < 0)
return ret;
return 0;
}
-static int imx6_pcie_link_up(struct pcie_port *pp)
+static int imx_pcie_link_up(struct pcie_port *pp)
{
return dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1) &
PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
}
-static struct pcie_host_ops imx6_pcie_host_ops = {
- .link_up = imx6_pcie_link_up,
- .host_init = imx6_pcie_host_init,
+static struct pcie_host_ops imx_pcie_host_ops = {
+ .link_up = imx_pcie_link_up,
+ .host_init = imx_pcie_host_init,
};
-static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
+static int imx6_add_pcie_port(struct imx_pcie *imx_pcie,
struct platform_device *pdev)
{
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
int ret;
}
ret = devm_request_irq(dev, pp->msi_irq,
- imx6_pcie_msi_handler,
+ imx_pcie_msi_handler,
IRQF_SHARED | IRQF_NO_THREAD,
- "mx6-pcie-msi", imx6_pcie);
+ "mx6-pcie-msi", imx_pcie);
if (ret) {
dev_err(dev, "failed to request MSI irq\n");
return ret;
}
pp->root_bus_nr = -1;
- pp->ops = &imx6_pcie_host_ops;
+ pp->ops = &imx_pcie_host_ops;
ret = dw_pcie_host_init(pp);
if (ret) {
static ssize_t imx_pcie_bar0_addr_info(struct device *dev,
struct device_attribute *devattr, char *buf)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct pcie_port *pp = &imx_pcie->pp;
return sprintf(buf, "imx-pcie-bar0-addr-info start 0x%08x\n",
readl(pp->dbi_base + PCI_BASE_ADDRESS_0));
struct device_attribute *attr, const char *buf, size_t count)
{
u32 bar_start;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct pcie_port *pp = &imx_pcie->pp;
sscanf(buf, "%x\n", &bar_start);
writel(bar_start, pp->dbi_base + PCI_BASE_ADDRESS_0);
static void imx_pcie_regions_setup(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct pcie_port *pp = &imx_pcie->pp;
- switch (imx6_pcie->variant) {
+ switch (imx_pcie->variant) {
case IMX8QM:
case IMX8QXP:
case IMX8MQ:
const char *buf, size_t count)
{
u32 memw_start;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
sscanf(buf, "%x\n", &memw_start);
- if (imx6_pcie->variant == IMX7D || imx6_pcie->variant == IMX6SX) {
+ if (imx_pcie->variant == IMX7D || imx_pcie->variant == IMX6SX) {
if (memw_start < 0x80000000 || memw_start > 0xb0000000) {
dev_err(dev, "Invalid memory start addr.\n");
dev_info(dev, "e.x: echo 0xb0000000 > /sys/...");
.attrs = imx_pcie_ep_attrs,
};
-static void imx6_pcie_setup_ep(struct pcie_port *pp)
+static void imx_pcie_setup_ep(struct pcie_port *pp)
{
int ret;
u32 val;
#ifdef CONFIG_PM_SLEEP
/* PM_TURN_OFF */
-static void pci_imx_pm_turn_off(struct imx6_pcie *imx6_pcie)
+static void pci_imx_pm_turn_off(struct imx_pcie *imx_pcie)
{
int i;
u32 dst, val;
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct pcie_port *pp = &imx_pcie->pp;
struct device *dev = pp->dev;
/* PM_TURN_OFF */
- switch (imx6_pcie->variant) {
+ switch (imx_pcie->variant) {
case IMX6SX:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF,
IMX6SX_GPR12_PCIE_PM_TURN_OFF);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
break;
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_PM_TURN_OFF,
IMX6Q_GPR12_PCIE_PM_TURN_OFF);
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_PM_TURN_OFF, 0);
break;
case IMX7D:
case IMX8MQ:
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
dst = IMX8MQ_SRC_PCIEPHY_RCR_OFFSET;
else
dst = IMX8MQ_SRC_PCIE2PHY_RCR_OFFSET;
- regmap_update_bits(imx6_pcie->reg_src, dst,
+ regmap_update_bits(imx_pcie->reg_src, dst,
IMX8MQ_PCIE_CTRL_APPS_TURNOFF,
IMX8MQ_PCIE_CTRL_APPS_TURNOFF);
- regmap_update_bits(imx6_pcie->reg_src, dst,
+ regmap_update_bits(imx_pcie->reg_src, dst,
IMX8MQ_PCIE_CTRL_APPS_TURNOFF,
0);
break;
case IMX8QXP:
case IMX8QM:
- dst = IMX8QM_CSR_PCIEA_OFFSET + imx6_pcie->ctrl_id * SZ_64K;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ dst = IMX8QM_CSR_PCIEA_OFFSET + imx_pcie->ctrl_id * SZ_64K;
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
dst + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_PM_XMT_TURNOFF,
IMX8QM_CTRL_PM_XMT_TURNOFF);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
dst + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_PM_XMT_TURNOFF,
0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
dst + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_READY_ENTR_L23,
IMX8QM_CTRL_READY_ENTR_L23);
/* check the L2 is entered or not. */
for (i = 0; i < 10000; i++) {
- regmap_read(imx6_pcie->iomuxc_gpr,
+ regmap_read(imx_pcie->iomuxc_gpr,
dst + IMX8QM_CSR_PCIE_STTS0_OFFSET,
&val);
if (val & IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2)
}
if ((val & IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2) == 0)
dev_err(dev, "PCIE%d can't enter into L2.\n",
- imx6_pcie->ctrl_id);
+ imx_pcie->ctrl_id);
break;
case IMX6Q:
dev_info(dev, "Info: don't support pm_turn_off yet.\n");
}
udelay(1000);
- if (gpio_is_valid(imx6_pcie->reset_gpio))
- gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0);
+ if (gpio_is_valid(imx_pcie->reset_gpio))
+ gpio_set_value_cansleep(imx_pcie->reset_gpio, 0);
}
static int pci_imx_suspend_noirq(struct device *dev)
{
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct pcie_port *pp = &imx_pcie->pp;
if (IS_ENABLED(CONFIG_PCI_MSI))
dw_pcie_msi_cfg_store(pp);
- pci_imx_pm_turn_off(imx6_pcie);
+ pci_imx_pm_turn_off(imx_pcie);
- if (unlikely(imx6_pcie->variant == IMX6Q)) {
+ if (unlikely(imx_pcie->variant == IMX6Q)) {
/*
* L2 can exit by 'reset' or Inband beacon (from remote EP)
* toggling phy_powerdown has same effect as 'inband beacon'
* So, toggle bit18 of GPR1, used as a workaround of errata
* "PCIe PCIe does not support L2 Power Down"
*/
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD,
IMX6Q_GPR1_PCIE_TEST_PD);
} else {
pci_imx_clk_disable(dev);
- if (imx6_pcie->variant == IMX8MQ)
- imx6_pcie_phy_pwr_dn(imx6_pcie);
+ if (imx_pcie->variant == IMX8MQ)
+ imx_pcie_phy_pwr_dn(imx_pcie);
/* Power down PCIe PHY. */
- if (imx6_pcie->pcie_phy_regulator != NULL)
- regulator_disable(imx6_pcie->pcie_phy_regulator);
- if (imx6_pcie->pcie_bus_regulator != NULL)
- regulator_disable(imx6_pcie->pcie_bus_regulator);
+ if (imx_pcie->pcie_phy_regulator != NULL)
+ regulator_disable(imx_pcie->pcie_phy_regulator);
+ if (imx_pcie->pcie_bus_regulator != NULL)
+ regulator_disable(imx_pcie->pcie_bus_regulator);
}
return 0;
static void pci_imx_ltssm_disable(struct device *dev)
{
u32 val;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
- switch (imx6_pcie->variant) {
+ switch (imx_pcie->variant) {
case IMX6Q:
case IMX6SX:
case IMX6QP:
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0);
break;
case IMX7D:
case IMX8MQ:
- if (imx6_pcie->ctrl_id == 0)
+ if (imx_pcie->ctrl_id == 0)
val = IMX8MQ_SRC_PCIEPHY_RCR_OFFSET;
else
val = IMX8MQ_SRC_PCIE2PHY_RCR_OFFSET;
- regmap_update_bits(imx6_pcie->reg_src, val,
+ regmap_update_bits(imx_pcie->reg_src, val,
IMX8MQ_PCIE_CTRL_APPS_EN,
0);
break;
case IMX8QM:
/* Bit4 of the CTRL2 */
val = IMX8QM_CSR_PCIEA_OFFSET
- + imx6_pcie->ctrl_id * SZ_64K;
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ + imx_pcie->ctrl_id * SZ_64K;
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_LTSSM_ENABLE, 0);
- regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ regmap_update_bits(imx_pcie->iomuxc_gpr,
val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
IMX8QM_CTRL_READY_ENTR_L23, 0);
break;
static int pci_imx_resume_noirq(struct device *dev)
{
int ret = 0;
- struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- struct pcie_port *pp = &imx6_pcie->pp;
+ struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
+ struct pcie_port *pp = &imx_pcie->pp;
- if (unlikely(imx6_pcie->variant == IMX6Q)) {
+ if (unlikely(imx_pcie->variant == IMX6Q)) {
/*
* L2 can exit by 'reset' or Inband beacon (from remote EP)
* toggling phy_powerdown has same effect as 'inband beacon'
* So, toggle bit18 of GPR1, used as a workaround of errata
* "PCIe PCIe does not support L2 Power Down"
*/
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 0);
} else {
pci_imx_ltssm_disable(dev);
- imx6_pcie_assert_core_reset(imx6_pcie);
- imx6_pcie_init_phy(imx6_pcie);
- ret = imx6_pcie_deassert_core_reset(imx6_pcie);
+ imx_pcie_assert_core_reset(imx_pcie);
+ imx_pcie_init_phy(imx_pcie);
+ ret = imx_pcie_deassert_core_reset(imx_pcie);
if (ret < 0)
return ret;
dw_pcie_msi_cfg_restore(pp);
pci_imx_ltssm_enable(dev);
- ret = imx6_pcie_wait_for_link(imx6_pcie);
+ ret = imx_pcie_wait_for_link(imx_pcie);
if (ret < 0)
dev_info(dev, "pcie link is down after resume.\n");
}
{
u32 irqs, offset;
struct pcie_port *pp = (struct pcie_port *)param;
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pp);
- offset = imx6_pcie->dma_unroll_offset;
+ offset = imx_pcie->dma_unroll_offset;
/* check write isr */
irqs = readl(pp->dbi_base + offset + DMA_WRITE_INT_STS);
unsigned int len)
{
u32 offset, doorbell, unroll_cal;
- struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pp);
if (pp == NULL)
return -EINVAL;
if (chl > MAX_PCIE_DMA_CHANNELS)
return -EINVAL;
- offset = imx6_pcie->dma_unroll_offset;
+ offset = imx_pcie->dma_unroll_offset;
/* enable dma engine, dir 1:read. 0:write. */
if (dir)
writel(DMA_READ_ENGINE_EN,
return 0;
}
-static int imx6_pcie_probe(struct platform_device *pdev)
+static int imx_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct imx6_pcie *imx6_pcie;
+ struct imx_pcie *imx_pcie;
struct pcie_port *pp;
struct device_node *np;
struct resource *res;
struct device_node *node = dev->of_node;
int ret;
- imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
- if (!imx6_pcie)
+ imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
+ if (!imx_pcie)
return -ENOMEM;
- pp = &imx6_pcie->pp;
+ pp = &imx_pcie->pp;
pp->dev = dev;
- imx6_pcie->variant =
- (enum imx6_pcie_variants)of_device_get_match_data(dev);
+ imx_pcie->variant =
+ (enum imx_pcie_variants)of_device_get_match_data(dev);
- if (of_property_read_u32(node, "hsio-cfg", &imx6_pcie->hsio_cfg))
- imx6_pcie->hsio_cfg = 0;
+ if (of_property_read_u32(node, "hsio-cfg", &imx_pcie->hsio_cfg))
+ imx_pcie->hsio_cfg = 0;
- if (of_property_read_u32(node, "ctrl-id", &imx6_pcie->ctrl_id))
- imx6_pcie->ctrl_id = 0;
+ if (of_property_read_u32(node, "ctrl-id", &imx_pcie->ctrl_id))
+ imx_pcie->ctrl_id = 0;
- if (of_property_read_u32(node, "cpu-base-addr", &imx6_pcie->cpu_base))
- imx6_pcie->cpu_base = 0;
- if (of_property_read_u32(node, "hard-wired", &imx6_pcie->hard_wired))
- imx6_pcie->hard_wired = 0;
+ if (of_property_read_u32(node, "cpu-base-addr", &imx_pcie->cpu_base))
+ imx_pcie->cpu_base = 0;
+ if (of_property_read_u32(node, "hard-wired", &imx_pcie->hard_wired))
+ imx_pcie->hard_wired = 0;
np = of_find_compatible_node(NULL, NULL, "fsl,imx-pcie-phy");
if (np != NULL) {
- imx6_pcie->phy_base = of_iomap(np, 0);
- WARN_ON(!imx6_pcie->phy_base);
+ imx_pcie->phy_base = of_iomap(np, 0);
+ WARN_ON(!imx_pcie->phy_base);
} else {
- imx6_pcie->phy_base = NULL;
+ imx_pcie->phy_base = NULL;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
return PTR_ERR(pp->dbi_base);
/* Fetch GPIOs */
- imx6_pcie->clkreq_gpio = of_get_named_gpio(node, "clkreq-gpio", 0);
- if (gpio_is_valid(imx6_pcie->clkreq_gpio)) {
- ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->clkreq_gpio,
+ imx_pcie->clkreq_gpio = of_get_named_gpio(node, "clkreq-gpio", 0);
+ if (gpio_is_valid(imx_pcie->clkreq_gpio)) {
+ ret = devm_gpio_request_one(&pdev->dev, imx_pcie->clkreq_gpio,
GPIOF_OUT_INIT_LOW, "PCIe CLKREQ");
if (ret) {
dev_err(&pdev->dev, "unable to get clkreq gpio\n");
return ret;
}
- } else if (imx6_pcie->clkreq_gpio == -EPROBE_DEFER) {
- return imx6_pcie->clkreq_gpio;
+ } else if (imx_pcie->clkreq_gpio == -EPROBE_DEFER) {
+ return imx_pcie->clkreq_gpio;
}
- imx6_pcie->dis_gpio = of_get_named_gpio(node, "disable-gpio", 0);
- if (gpio_is_valid(imx6_pcie->dis_gpio)) {
- ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->dis_gpio,
+ imx_pcie->dis_gpio = of_get_named_gpio(node, "disable-gpio", 0);
+ if (gpio_is_valid(imx_pcie->dis_gpio)) {
+ ret = devm_gpio_request_one(&pdev->dev, imx_pcie->dis_gpio,
GPIOF_OUT_INIT_HIGH, "PCIe DIS");
if (ret) {
dev_err(&pdev->dev, "unable to get disable gpio\n");
return ret;
}
- } else if (imx6_pcie->dis_gpio == -EPROBE_DEFER) {
- return imx6_pcie->dis_gpio;
+ } else if (imx_pcie->dis_gpio == -EPROBE_DEFER) {
+ return imx_pcie->dis_gpio;
}
- imx6_pcie->power_on_gpio = of_get_named_gpio(node, "power-on-gpio", 0);
- if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
+ imx_pcie->power_on_gpio = of_get_named_gpio(node, "power-on-gpio", 0);
+ if (gpio_is_valid(imx_pcie->power_on_gpio)) {
ret = devm_gpio_request_one(&pdev->dev,
- imx6_pcie->power_on_gpio,
+ imx_pcie->power_on_gpio,
GPIOF_OUT_INIT_LOW,
"PCIe power enable");
if (ret) {
dev_err(&pdev->dev, "unable to get power-on gpio\n");
return ret;
}
- } else if (imx6_pcie->power_on_gpio == -EPROBE_DEFER) {
- return imx6_pcie->power_on_gpio;
+ } else if (imx_pcie->power_on_gpio == -EPROBE_DEFER) {
+ return imx_pcie->power_on_gpio;
}
- imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
- imx6_pcie->gpio_active_high = of_property_read_bool(node,
+ imx_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
+ imx_pcie->gpio_active_high = of_property_read_bool(node,
"reset-gpio-active-high");
- if (gpio_is_valid(imx6_pcie->reset_gpio)) {
- ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
- imx6_pcie->gpio_active_high ?
+ if (gpio_is_valid(imx_pcie->reset_gpio)) {
+ ret = devm_gpio_request_one(dev, imx_pcie->reset_gpio,
+ imx_pcie->gpio_active_high ?
GPIOF_OUT_INIT_HIGH :
GPIOF_OUT_INIT_LOW,
"PCIe reset");
dev_err(dev, "unable to get reset gpio\n");
return ret;
}
- } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
- return imx6_pcie->reset_gpio;
+ } else if (imx_pcie->reset_gpio == -EPROBE_DEFER) {
+ return imx_pcie->reset_gpio;
}
- imx6_pcie->epdev_on = devm_regulator_get(&pdev->dev, "epdev_on");
- if (IS_ERR(imx6_pcie->epdev_on)) {
- if (PTR_ERR(imx6_pcie->epdev_on) == -EPROBE_DEFER)
+ imx_pcie->epdev_on = devm_regulator_get(&pdev->dev, "epdev_on");
+ if (IS_ERR(imx_pcie->epdev_on)) {
+ if (PTR_ERR(imx_pcie->epdev_on) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_info(dev, "no ep regulator found\n");
- imx6_pcie->epdev_on = NULL;
+ imx_pcie->epdev_on = NULL;
} else {
- ret = regulator_enable(imx6_pcie->epdev_on);
+ ret = regulator_enable(imx_pcie->epdev_on);
if (ret)
dev_err(dev, "failed to enable the epdev_on regulator\n");
}
/* Fetch clocks */
- imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
- if (IS_ERR(imx6_pcie->pcie_phy)) {
+ imx_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
+ if (IS_ERR(imx_pcie->pcie_phy)) {
dev_err(dev, "pcie_phy clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_phy);
+ return PTR_ERR(imx_pcie->pcie_phy);
}
- imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
- if (IS_ERR(imx6_pcie->pcie_bus)) {
+ imx_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
+ if (IS_ERR(imx_pcie->pcie_bus)) {
dev_err(dev, "pcie_bus clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_bus);
+ return PTR_ERR(imx_pcie->pcie_bus);
}
- if (of_property_read_u32(node, "ext_osc", &imx6_pcie->ext_osc) < 0)
- imx6_pcie->ext_osc = 0;
+ if (of_property_read_u32(node, "ext_osc", &imx_pcie->ext_osc) < 0)
+ imx_pcie->ext_osc = 0;
- if (imx6_pcie->ext_osc && (imx6_pcie->variant == IMX6QP)) {
+ if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP)) {
/* Change the pcie_bus clock to pcie external OSC */
- imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_ext");
- if (IS_ERR(imx6_pcie->pcie_bus)) {
+ imx_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_ext");
+ if (IS_ERR(imx_pcie->pcie_bus)) {
dev_err(&pdev->dev,
"pcie_bus clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_bus);
+ return PTR_ERR(imx_pcie->pcie_bus);
}
- imx6_pcie->pcie_ext_src = devm_clk_get(&pdev->dev,
+ imx_pcie->pcie_ext_src = devm_clk_get(&pdev->dev,
"pcie_ext_src");
- if (IS_ERR(imx6_pcie->pcie_ext_src)) {
+ if (IS_ERR(imx_pcie->pcie_ext_src)) {
dev_err(&pdev->dev,
"pcie_ext_src clk src missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_ext_src);
+ return PTR_ERR(imx_pcie->pcie_ext_src);
}
}
- imx6_pcie->pcie = devm_clk_get(dev, "pcie");
- if (IS_ERR(imx6_pcie->pcie)) {
+ imx_pcie->pcie = devm_clk_get(dev, "pcie");
+ if (IS_ERR(imx_pcie->pcie)) {
dev_err(dev, "pcie clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie);
+ return PTR_ERR(imx_pcie->pcie);
}
- if (imx6_pcie->variant == IMX6QP) {
- imx6_pcie->pcie_bus_regulator = devm_regulator_get(pp->dev,
+ if (imx_pcie->variant == IMX6QP) {
+ imx_pcie->pcie_bus_regulator = devm_regulator_get(pp->dev,
"pcie-bus");
- if (PTR_ERR(imx6_pcie->pcie_bus_regulator) == -EPROBE_DEFER)
+ if (PTR_ERR(imx_pcie->pcie_bus_regulator) == -EPROBE_DEFER)
return -EPROBE_DEFER;
- if (IS_ERR(imx6_pcie->pcie_bus_regulator))
- imx6_pcie->pcie_bus_regulator = NULL;
+ if (IS_ERR(imx_pcie->pcie_bus_regulator))
+ imx_pcie->pcie_bus_regulator = NULL;
} else {
- imx6_pcie->pcie_bus_regulator = NULL;
+ imx_pcie->pcie_bus_regulator = NULL;
}
/* Grab GPR config register range */
- if (imx6_pcie->variant == IMX7D) {
- imx6_pcie->iomuxc_gpr =
+ if (imx_pcie->variant == IMX7D) {
+ imx_pcie->iomuxc_gpr =
syscon_regmap_lookup_by_compatible
("fsl,imx7d-iomuxc-gpr");
- imx6_pcie->reg_src =
+ imx_pcie->reg_src =
syscon_regmap_lookup_by_compatible("fsl,imx7d-src");
- if (IS_ERR(imx6_pcie->reg_src)) {
+ if (IS_ERR(imx_pcie->reg_src)) {
dev_err(&pdev->dev,
"imx7d pcie phy src missing or invalid\n");
- return PTR_ERR(imx6_pcie->reg_src);
+ return PTR_ERR(imx_pcie->reg_src);
}
- imx6_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
+ imx_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
"pcie-phy");
- } else if (imx6_pcie->variant == IMX8MQ) {
- imx6_pcie->iomuxc_gpr =
+ } else if (imx_pcie->variant == IMX8MQ) {
+ imx_pcie->iomuxc_gpr =
syscon_regmap_lookup_by_compatible
("fsl,imx8mq-iomuxc-gpr");
- imx6_pcie->reg_src =
+ imx_pcie->reg_src =
syscon_regmap_lookup_by_compatible("fsl,imx8mq-src");
- if (IS_ERR(imx6_pcie->reg_src)) {
+ if (IS_ERR(imx_pcie->reg_src)) {
dev_err(&pdev->dev,
"imx8mq pcie phy src missing or invalid\n");
- return PTR_ERR(imx6_pcie->reg_src);
+ return PTR_ERR(imx_pcie->reg_src);
}
- imx6_pcie->reg_gpc =
+ imx_pcie->reg_gpc =
syscon_regmap_lookup_by_compatible("fsl,imx8mq-gpc");
- if (IS_ERR(imx6_pcie->reg_gpc)) {
+ if (IS_ERR(imx_pcie->reg_gpc)) {
dev_err(&pdev->dev,
"imx8mq pcie phy src missing or invalid\n");
- return PTR_ERR(imx6_pcie->reg_gpc);
+ return PTR_ERR(imx_pcie->reg_gpc);
}
- } else if (imx6_pcie->variant == IMX6SX) {
- imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
+ } else if (imx_pcie->variant == IMX6SX) {
+ imx_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
"pcie_inbound_axi");
- if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
+ if (IS_ERR(imx_pcie->pcie_inbound_axi)) {
dev_err(&pdev->dev,
"pcie clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_inbound_axi);
+ return PTR_ERR(imx_pcie->pcie_inbound_axi);
}
- imx6_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
+ imx_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
"pcie-phy");
- imx6_pcie->iomuxc_gpr =
+ imx_pcie->iomuxc_gpr =
syscon_regmap_lookup_by_compatible
("fsl,imx6sx-iomuxc-gpr");
- } else if (imx6_pcie->variant == IMX8QM
- || imx6_pcie->variant == IMX8QXP) {
- imx6_pcie->pcie_per = devm_clk_get(dev, "pcie_per");
- if (IS_ERR(imx6_pcie->pcie_per)) {
+ } else if (imx_pcie->variant == IMX8QM
+ || imx_pcie->variant == IMX8QXP) {
+ imx_pcie->pcie_per = devm_clk_get(dev, "pcie_per");
+ if (IS_ERR(imx_pcie->pcie_per)) {
dev_err(dev, "pcie_per clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_per);
+ return PTR_ERR(imx_pcie->pcie_per);
}
- imx6_pcie->iomuxc_gpr =
+ imx_pcie->iomuxc_gpr =
syscon_regmap_lookup_by_phandle(node, "hsio");
- imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
+ imx_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
"pcie_inbound_axi");
- if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
+ if (IS_ERR(imx_pcie->pcie_inbound_axi)) {
dev_err(&pdev->dev,
"pcie clock source missing or invalid\n");
- return PTR_ERR(imx6_pcie->pcie_inbound_axi);
+ return PTR_ERR(imx_pcie->pcie_inbound_axi);
}
} else {
- imx6_pcie->iomuxc_gpr =
+ imx_pcie->iomuxc_gpr =
syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
}
- if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
+ if (IS_ERR(imx_pcie->iomuxc_gpr)) {
dev_err(dev, "unable to find iomuxc registers\n");
- return PTR_ERR(imx6_pcie->iomuxc_gpr);
+ return PTR_ERR(imx_pcie->iomuxc_gpr);
}
/* Grab PCIe PHY Tx Settings */
if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
- &imx6_pcie->tx_deemph_gen1))
- imx6_pcie->tx_deemph_gen1 = 20;
+ &imx_pcie->tx_deemph_gen1))
+ imx_pcie->tx_deemph_gen1 = 20;
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
- &imx6_pcie->tx_deemph_gen2_3p5db))
- imx6_pcie->tx_deemph_gen2_3p5db = 20;
+ &imx_pcie->tx_deemph_gen2_3p5db))
+ imx_pcie->tx_deemph_gen2_3p5db = 20;
if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
- &imx6_pcie->tx_deemph_gen2_6db))
- imx6_pcie->tx_deemph_gen2_6db = 20;
+ &imx_pcie->tx_deemph_gen2_6db))
+ imx_pcie->tx_deemph_gen2_6db = 20;
if (of_property_read_u32(node, "fsl,tx-swing-full",
- &imx6_pcie->tx_swing_full))
- imx6_pcie->tx_swing_full = 115;
+ &imx_pcie->tx_swing_full))
+ imx_pcie->tx_swing_full = 115;
if (of_property_read_u32(node, "fsl,tx-swing-low",
- &imx6_pcie->tx_swing_low))
- imx6_pcie->tx_swing_low = 115;
+ &imx_pcie->tx_swing_low))
+ imx_pcie->tx_swing_low = 115;
/* Limit link speed */
ret = of_property_read_u32(node, "fsl,max-link-speed",
- &imx6_pcie->link_gen);
+ &imx_pcie->link_gen);
if (ret)
- imx6_pcie->link_gen = 1;
+ imx_pcie->link_gen = 1;
- platform_set_drvdata(pdev, imx6_pcie);
+ platform_set_drvdata(pdev, imx_pcie);
if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
- && (imx6_pcie->hard_wired == 0)) {
+ && (imx_pcie->hard_wired == 0)) {
int i = 0, irq;
void *test_reg1, *test_reg2;
dma_addr_t test_reg1_dma, test_reg2_dma;
}
pp->mem_base = pp->mem->start;
- pp->ops = &imx6_pcie_host_ops;
+ pp->ops = &imx_pcie_host_ops;
dev_info(dev, " try to initialize pcie ep.\n");
- ret = imx6_pcie_host_init(pp);
+ ret = imx_pcie_host_init(pp);
if (ret) {
dev_info(dev, " fail to initialize pcie ep.\n");
return ret;
}
- imx6_pcie_setup_ep(pp);
- platform_set_drvdata(pdev, imx6_pcie);
+ imx_pcie_setup_ep(pp);
+ platform_set_drvdata(pdev, imx_pcie);
imx_pcie_regions_setup(dev);
/*
* before LTSSM enable is set
* .
*/
- if (imx6_pcie->variant == IMX6SX)
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+ if (imx_pcie->variant == IMX6SX)
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
BIT(19), 0 << 19);
/* assert LTSSM enable */
val = readl(pp->dbi_base + DMA_CTRL_VIEWPORT_OFF);
if (val == 0xffffffff)
- imx6_pcie->dma_unroll_offset =
+ imx_pcie->dma_unroll_offset =
DMA_UNROLL_CDM_OFFSET - DMA_REG_OFFSET;
else
- imx6_pcie->dma_unroll_offset = 0;
+ imx_pcie->dma_unroll_offset = 0;
}
if (unlikely(dma_en == 0)) {
if (ret)
return -EINVAL;
- ret = imx6_add_pcie_port(imx6_pcie, pdev);
+ ret = imx6_add_pcie_port(imx_pcie, pdev);
if (ret < 0) {
if (IS_ENABLED(CONFIG_PCI_IMX6_COMPLIANCE_TEST)) {
/* The PCIE clocks wouldn't be turned off */
return ret;
}
if (IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)
- && (imx6_pcie->hard_wired == 0))
+ && (imx_pcie->hard_wired == 0))
imx_pcie_regions_setup(&pdev->dev);
}
return 0;
}
-static void imx6_pcie_shutdown(struct platform_device *pdev)
+static void imx_pcie_shutdown(struct platform_device *pdev)
{
- struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
+ struct imx_pcie *imx_pcie = platform_get_drvdata(pdev);
/* bring down link, so bootloader gets clean state in case of reboot */
- if (imx6_pcie->variant == IMX6Q)
- imx6_pcie_assert_core_reset(imx6_pcie);
+ if (imx_pcie->variant == IMX6Q)
+ imx_pcie_assert_core_reset(imx_pcie);
}
-static const struct of_device_id imx6_pcie_of_match[] = {
+static const struct of_device_id imx_pcie_of_match[] = {
{ .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
{ .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
{ .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
{},
};
-static struct platform_driver imx6_pcie_driver = {
+static struct platform_driver imx_pcie_driver = {
.driver = {
- .name = "imx6q-pcie",
- .of_match_table = imx6_pcie_of_match,
+ .name = "imx-pcie",
+ .of_match_table = imx_pcie_of_match,
.pm = &pci_imx_pm_ops,
},
- .probe = imx6_pcie_probe,
- .shutdown = imx6_pcie_shutdown,
+ .probe = imx_pcie_probe,
+ .shutdown = imx_pcie_shutdown,
};
-static int __init imx6_pcie_init(void)
+static int __init imx_pcie_init(void)
{
#ifdef CONFIG_ARM
/*
* Since probe() can be deferred we need to make sure that
* hook_fault_code is not called after __init memory is freed
- * by kernel and since imx6q_pcie_abort_handler() is a no-op,
+ * by kernel and since imx_pcie_abort_handler() is a no-op,
* we can install the handler here without risking it
* accessing some uninitialized driver state.
*/
- hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
+ hook_fault_code(16 + 6, imx_pcie_abort_handler, SIGBUS, 0,
"imprecise external abort");
#endif
- return platform_driver_register(&imx6_pcie_driver);
+ return platform_driver_register(&imx_pcie_driver);
}
-device_initcall(imx6_pcie_init);
+device_initcall(imx_pcie_init);
projects / linux.git / commitdiff